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Vertically Extended Drain Double Gate Si1−xGex Source Tunnel FET : Proposal & Investigation For Optimized Device Performance

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Abstract

This paper reports an unique approach to suppress ambipolarity and enhance drive current in tunnel field effect transistor (TFET) by incorporating vertically extending drain in double gate Si1−xGex source TFET. This structure has dual source extending laterally on both sides of the channel with vertically extended drain over the T-shaped channel (VD-DG-Si1−xGexS-TFET). Our study is based on calibrated exhaustive 2-D TCAD simulations. It advocates that the device performance is not only retained but significantly enhanced even by deploying only double gate instead of quadruple gate with Si1−xGex sources. Further the drive current can be significantly increased by optimizing the mole fraction (x) in Si1−xGex source. Our study reveals that the average subthreshold slope (SSavg) is 23.98 m V/dec (point SS (SSpoint) is 12.7 m V/dec with sub-60 m V/dec point SS for 107 orders of current change), drive current (ION) is 2.73× 10− 4 A/um and 46% improvement in transconductance as compared to the earlier reported drain engineered quardruple gate TFET. Further the device sensitivity analysis with respect to gate oxide dielectric constant, gate metal work-function, temperature and germanium mole fraction variation is also analyzed here. Moreover, in terms of device analog behaviour, the cut off frequency (ft) is reported as 38.93 GHz and 140% increment in gain bandwidth product (GWB) as compared to its quardruple gate alternative. This study proves the potentials of considered device structure as a promising candidate for ultra low power analog/RF and digital logic applications.

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Acknowledgement

The authors are grateful to the National Institute of Technology, Raipur for providing the computational resources.

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Authors and Affiliations

  1. Microelectronics, VLSI Design Lab, National Institute of Technology Patna, Patna, India

    Anand Raj, Sangeeta Singh, Kumari Nibha Priyadarshani & Rajeev Arya

  2. National Institute of Technology Raipur, Raipur, India

    Alok Naugarhiya

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  1. Anand Raj
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  2. Sangeeta Singh
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  3. Kumari Nibha Priyadarshani
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  5. Alok Naugarhiya
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Correspondence to Sangeeta Singh.

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Raj, A., Singh, S., Priyadarshani, K.N. et al. Vertically Extended Drain Double Gate Si1−xGex Source Tunnel FET : Proposal & Investigation For Optimized Device Performance. Silicon 13, 2589–2604 (2021). https://doi.org/10.1007/s12633-020-00603-1

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