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Performance Analysis of Channel and Inner Gate Engineered GAA Nanowire FET

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Abstract

The present paper presents a graded channel NWFET using a doping-less technique with a core gate covering the channel and drain region. The graded channel and inner gate further suppresses the short channel effects and enhances the device performance capabilities. The performance metrics of the aforementioned device are calculated and compared with Charge Plasma and junctionless GAA-NWFET. The results show that our proposed structure exhibits improved Ion, Ioff, subthreshold slope (SS) and drain induced barrier lowering (DIBL). The graded channel has been effectively created by means of the charge plasma technique inorder to decrease the fabrication cumbersomeness. To enhance the channel controllability further, using an inner gate is proposed. Our proposed device aims at making MOSFET more striking to carry on with the scaling trends.

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Authors and Affiliations

  1. Department of ECE, National Institute of Technology Delhi, Delhi, India

    Ashima & D. Vaithiyanathan

  2. Department of ECE, NITTTR Chandigarh, Chandigarh, India

    Balwinder Raj

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  1. Ashima
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  2. D. Vaithiyanathan
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  3. Balwinder Raj
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Correspondence to Ashima.

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Ashima, Vaithiyanathan, D. & Raj, B. Performance Analysis of Channel and Inner Gate Engineered GAA Nanowire FET. Silicon 13, 1863–1869 (2021). https://doi.org/10.1007/s12633-020-00575-2

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