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Dual-Channel Junctionless FETs for Improved Analog/RF Performance

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Abstract

A dual-channel single gate junctionless FET (DCJLT) is investigated to improve the analog/RF performance. The gate of proposed structure is placed in a vertical trench and two channels are taken on both sides of the gate. The proposed device is studied with moderate and heavily doped drain concentrations which are named as MDD-DCJLT and HDD-DCJLT, respectively. The performance parameters of both devices are evaluated and compared in terms of drain current (IDS), transconductance (gm), transconductance generation efficiency (gm/IDS), unity-gain cut-off frequency (fT) and maximum oscillation frequency (fmax) using 2D numerical simulations in a TCAD tool (ATLAS). The proposed HDD-DCJLT is demonstrated to offer peak gm, fT and fmax of 2304 μS/μm, 548 GHz and 830 GHz, respectively at gate length of 20 nm. Thus, the proposed structure is a suitable choice for analog/RF applications.

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Authors and Affiliations

  1. Department of Electronics, Communication Engineering, G. B. Pant Institute of Engineering and Technology, Pauri Garhwal, Uttarakhand, 246 194, India

    Aanchal Garg, Yashvir Singh & Balraj Singh

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  1. Aanchal Garg
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  2. Yashvir Singh
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  3. Balraj Singh
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Correspondence to Balraj Singh.

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Garg, A., Singh, Y. & Singh, B. Dual-Channel Junctionless FETs for Improved Analog/RF Performance. Silicon 13, 1499–1507 (2021). https://doi.org/10.1007/s12633-020-00545-8

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