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Design of a high speed Vedic multiplier and square architecture based on Yavadunam Sutra

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Abstract

In current day situation we come across numerous mathematical challenges. This could be overwhelmed by the Vedic Mathematics. Vedic Mathematics is an ancient approach to solve problems in a rapid manner. In this paper the design of a novel Vedic square and multiplier architecture based on Yavadunam Sutra is proposed. Yavadunam is a squaring sutra of the Vedic Mathematics. We have designed a generic architecture for this squaring sutra and have designed a high speed Vedic binary multiplier architecture using the principles of Yavadunam sutra. The proposed multiplier offers significant improvement in speed. Xilinx Spartan FPGA is used to design and realize the architecture and the Synopsys device with 90 nm and 180 nm technology is used to synthesize the same.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, J.K.K. Munirajah College of Technology, Gobi, Erode, India

    A Deepa

  2. Department of Electronics and Communication Engineering, Nandha Engineering College, Erode, India

    C N Marimuthu

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  1. A Deepa
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  2. C N Marimuthu
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Correspondence to A Deepa.

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Deepa, A., Marimuthu, C.N. Design of a high speed Vedic multiplier and square architecture based on Yavadunam Sutra. Sādhanā 44, 197 (2019). https://doi.org/10.1007/s12046-019-1180-3

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  • DOI: https://doi.org/10.1007/s12046-019-1180-3

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