Skip to main content
Log in

A novel architecture for ahead branch prediction

  • Research Article
  • Published:
Frontiers of Computer Science Aims and scope Submit manuscript

Abstract

In theory, branch predictors with more complicated algorithms and larger data structures provide more accurate predictions. Unfortunately, overly large structures and excessively complicated algorithms cannot be implemented because of their long access delay. To date, many strategies have been proposed to balance delay with accuracy, but none has completely solved the issue. The architecture for ahead branch prediction (A2BP) separates traditional predictors into two parts. First is a small table located at the front-end of the pipeline, which makes the prediction brief enough even for some aggressive processors. Second, operations on complicated algorithms and large data structures for accurate predictions are all moved to the back-end of the pipeline. An effective mechanism is introduced for ahead branch prediction in the back-end and small table update in the front. To substantially improve prediction accuracy, an indirect branch prediction algorithm based on branch history and target path (BHTP) is implemented in A2BP. Experiments with the standard performance evaluation corporation (SPEC) benchmarks on gem5/SimpleScalar simulators demonstrate that A2BP improves average performance by 2.92% compared with a commonly used branch target buffer-based predictor. In addition, indirect branch misses with the BHTP algorithm are reduced by an average of 28.98% compared with the traditional algorithm.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. Seznec A. The L-TAGE branch predictor. Journal of Instruction-Level Parallelism, 2007, http://www.jilp.org/vol9/v9paper6.pdf

    Google Scholar 

  2. Srinivasam R, Frachtenberg E, Lubeck O. An idealistic Neuro-PPM branch predictor. Journal of Instruction-Level Parallelism, 2007, http://www.jilp.org/vol9/v9paper8.pdf

    Google Scholar 

  3. Jimenez D A, Keckler S W, Lin C. The impact of delay on the design of branch predictors. In: Proceedings of the 33rd Annual ACM/IEEE International Symposium on Microarchitecture (MICRO’00). 2000, 67–76

    Chapter  Google Scholar 

  4. Burcea I, Moshovos A. Phantom-BTB: a virtualized branch target buffer design. In: Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’09). 2009, 313–324

    Chapter  Google Scholar 

  5. Jimenez D A. Reconsidering complex branch predictors. In: Proceedings of the 9th International Symposium on High-Performance Computer Architecture (HPCA’03). 2003, 43–52

    Google Scholar 

  6. Agarwal V, Hrishikesh M, Keckler S W. Clock rate versus IPC: the end of the road for conventional microarchitecture. In: Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA’00). 2000, 248–259

    Google Scholar 

  7. Burcea I, Somogyi S, Moshovos A. Predictor virtualization. In: Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’ 09). 2008, 157–167

    Chapter  Google Scholar 

  8. Seznec A, Michaud P. A case for (partially)-tagged geometric history length predictors. Journal of Instruction-Level Parallelism, http://www.jilp.org/vol8/v8paper1.pdf

  9. Seznec A, Fraboulet A. Effective ahead pipelining of instruction block address generation. In: Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA’03). 2003, 241–252

    Google Scholar 

  10. Seznec A, Felix S, Krishnan V. Design tradeoffs for the alpha EV8 conditional branch predictor. In: Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA’02). 2002, 295–306

    Chapter  Google Scholar 

  11. Santana O J, Ramirez A, Valero M. Latency tolerant branch predictors. In: Proceedings of Innovative Architecture for Future Generation High-performance Processors and Systems. 2003, 30–39

    Google Scholar 

  12. Joao J A, Mutlu O, Kim H. Improving the performance of objectoriented languages with dynamic predication of indirect jumps. In: Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’ 08). 2008, 80–90

    Chapter  Google Scholar 

  13. Li T, Bhargava R, John L K. Adapting branch-target buffer to improve the target predictability of java code. ACM Transactions on Architecture and Code Optimization, 2005, 2(2): 109–130

    Article  MATH  Google Scholar 

  14. Joao J A, Mutlu O, Kim H. Dynamic prediction of indirect jumps. IEEE Computer Architecture Letters, 2007, 6(2): 25–28

    Article  Google Scholar 

  15. Binkert N, Beckmann B, Black G. The gem5 simulator. ACM SIGARCH Computer Architecture News, 2011, 39(2): 1–7

    Article  Google Scholar 

  16. Nathan B L, Ronald D G, Lisa H R. The M5 simulator: modeling networked Systems. IEEE Micro Magazine, 2006, 26(4): 52–60

    Article  Google Scholar 

  17. Milo M K, Daniel S J, Bradford B M. Multifacet’s general execution-driven multiprocessor simulator (GEMS) toolset. ACM SIGARCH Computer Architecture News, 2005, 33(4): 92–99

    Article  Google Scholar 

  18. Austin T, Larson E, Ernst D. Simple Scalar: an infrastructure for computer system modeling. IEEE Micro Magazine, 2002, 35(2): 59–67

    Article  Google Scholar 

  19. Guthaus M R, Ringenberg J S, Ernst D. MiBench: a free, commercially representative embedded benchmark suite. In: Proceedings of the 2001 IEEE International Workshop on Workload Characterization. 2001, 3–14

    Google Scholar 

  20. Kim H, Joao J A, Mutlu O. VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization. In: Proceedings of the 34th Annual International Symposium on Computer Architecture (ISCA’07). 2007, 424–435

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Wenbing Jin.

Additional information

Wenbing Jin received his BS from Beijing Institute of Technology in 1990, and his MS from Taiyuan University of Technology in 2006. He is a senior engineer with North Automatic Control Technology Institute, and is currently a PhD candidate of Beijing Institute of Technology. His research interests include computer architecture, parallel computing, and artificial intelligence. He is a member of ACM.

Feng Shi received his BE in Physics in 1983 from Peking University and received his PhD from Beijing Institute of Technology, in 1999. He is currently a professor with the School of Computer Science and Technology, Beijing Institute of Technology. His research focuses on parallel computing and computer architecture.

Qiugui Song received his BS from North University of China in 2002. He is a senior engineer with North Automatic Control Technology Institute. His research interests include computer architecture and embedded systems.

Yang Zhang is a lecturer with Hebei University of Science and Technology, and currently a PhD candidate of Beijing Institute of Technology. His research interests include computer architecture and high-performance computing.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Jin, W., Shi, F., Song, Q. et al. A novel architecture for ahead branch prediction. Front. Comput. Sci. 7, 914–923 (2013). https://doi.org/10.1007/s11704-013-2260-x

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11704-013-2260-x

Keywords

Navigation