Abstract
This paper describes novel multibit static random-access memories (SRAMs) implemented using four-channel spatial wavefunction switched field-effect transistors (SWS FETs) with Ge quantum wells and ZnSSe barriers. A two-bit SRAM cell consists of two back-to-back connected four-channel SWS FETs, where each SWS FET serves as a quaternary inverter. This architecture results in a reduction of the field-effect transistor (FET) count by 75% and data interconnect density by 50%. The designed two-bit SRAM cell is simulated using Berkeley short-channel insulated-gate field-effect transistor equivalent-channel models (for 25-nm FETs). In addition, the binary interface logic and conversion circuitry are designed to integrate the SWS SRAM technology. Our motivation is to stack up multiple bits on a single SRAM cell without multiplying the transistor count. The concept of spatial wavefunction switching (SWS) in the FET structure has been verified experimentally for two- and four-well structures. Quantum simulations exhibiting SWS in four-well Ge SWS FET structures, using the ZnSe/ZnS/ZnMgS/ZnSe gate insulator, are presented. These structures offer higher contrast than Si-SiGe SWS FETs.
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Gogna, P., Suarez, E., Lingalugari, M. et al. Ge-ZnSSe Spatial Wavefunction Switched (SWS) FETs to Implement Multibit SRAMs and Novel Quaternary Logic. J. Electron. Mater. 42, 3337–3343 (2013). https://doi.org/10.1007/s11664-013-2762-1
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DOI: https://doi.org/10.1007/s11664-013-2762-1