Strain Reduction in Selectively Grown CdTe by MBE on Nanopatterned Silicon on Insulator (SOI) Substrates

Abstract

Silicon-based substrates for the epitaxy of HgCdTe are an attractive low-cost choice for monolithic integration of infrared detectors with mature Si technology and high yield. However, progress in heteroepitaxy of CdTe/Si (for subsequent growth of HgCdTe) is limited by the high lattice and thermal mismatch, which creates strain at the heterointerface that results in a high density of dislocations. Previously we have reported on theoretical modeling of strain partitioning between CdTe and Si on nanopatterned silicon on insulator (SOI) substrates. In this paper, we present an experimental study of CdTe epitaxy on nanopatterned (SOI). SOI (100) substrates were patterned with interferometric lithography and reactive ion etching to form a two-dimensional array of silicon pillars with ∼250 nm diameter and 1 μm pitch. MBE was used to grow CdTe selectively on the silicon nanopillars. Selective growth of CdTe was confirmed by scanning electron microscopy (SEM), atomic force microscopy (AFM), and X-ray photoelectron spectroscopy (XPS). Coalescence of CdTe on the silicon nanoislands has been observed from the SEM characterization. Selective growth was achieved with a two-step growth process involving desorption of the nucleation layer followed by regrowth of CdTe at a rate of 0.2 Å s⁻¹. Strain measurements by Raman spectroscopy show a comparable Raman shift (2.7 ± 2 cm⁻¹ from the bulk value of 170 cm⁻¹) in CdTe grown on nanopatterned SOI and planar silicon (Raman shift of 4.4 ± 2 cm⁻¹), indicating similar strain on the nanopatterned substrates.