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A single-cycle parallel multi-slice connected components analysis hardware architecture

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Abstract

In this paper, a memory-efficient architecture for single-pass connected components analysis suited for high-throughput embedded image processing systems is proposed which achieves a speedup by partitioning the image into slices. Although global data dependencies of image segments spanning several image slices exist, a temporal and spatial local algorithm is proposed, together with a suited FPGA hardware architecture processing pixel data at low latency. The low latency of the proposed architecture allows reuse of labels associated with the image objects. This reduces the amount of memory by a factor of more than 5 in the considered implementations which is a significant contribution since memory is a critical resource in embedded image processing on FPGAs. Therefore, a significantly higher bandwidth of pixel data can be processed with this architecture compared to the state-of-the-art architectures using the same amount of hardware resources.

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Acknowledgments

The authors would like to thank the German Research Foundation (DFG) for the financial support. This work was carried out within the research Project Si 586 7/1 which belongs to the priority program DFG-SPP 1423 Prozess-Spray.

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Authors and Affiliations

  1. University of Stuttgart, Stuttgart, Germany

    Michael J. Klaiber & Sven Simon

  2. Massey University, Palmerston North, New Zealand

    Donald G. Bailey

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  1. Michael J. Klaiber
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  2. Donald G. Bailey
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  3. Sven Simon
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Klaiber, M.J., Bailey, D.G. & Simon, S. A single-cycle parallel multi-slice connected components analysis hardware architecture. J Real-Time Image Proc 16, 1165–1175 (2019). https://doi.org/10.1007/s11554-016-0610-2

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  • DOI: https://doi.org/10.1007/s11554-016-0610-2

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