Optimization of speeded-up robust feature algorithm for hardware implementation

Abstract

Speeded-Up Robust Feature (SURF) is a widely-used robust local gradient feature detection and description algorithm. The algorithm itself can be implemented easily on general-purpose processors. However, the software implementation of SURF cannot achieve a performance high enough to meet the practical real-time requirements. And what is more, the huge data storage and the floating point operation of SURF algorithm make it hard and onerous to design and verify corresponding hardware implementation. This paper customized a SURF algorithm for hardware implementation, which combined several optimization methods in previous literature and three approaches (named Word Length Reduction (WLR), Low Bits Abandon(LBA), and Sampling Radius Reduction (SRR)). The computation operations of the simplified and optimized SURF (P-SURF) were reduced by 50% compared with the original SURF. At the same time, the Recall and Precision of the SURF feature descriptor are only dropped by 0.31 on average in the typical testing set, which are within an acceptable accuracy range. P-SURF has been implemented on hardware using TSMC 65 nm process, and the architecture of the whole system mainly contains four modules, including Integral Image Generator, IPoint Detector, IPoint Orientation Assigner, and IPoint Feature Vector Extractor. The chip size is 3.4 × 4 mm². The power usage is less than 220mW according to the Synopsys Prime time while extracting IPoints in a video input of VGA (640 × 480) 172 fps operating at 200 MHz. The performance is better than the results reported in literature.