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On the Development and Optimization of HEVC Video Decoders Using High-Level Dataflow Modeling

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Abstract

With the emergence of the High Efficiency Video Coding (HEVC) standard, a dataflow description of the decoder part was developed as part of the MPEG-B standard. This dataflow description presented modest framerate results which led us to propose methodologies to improve the performance. In this paper, we introduce architectural improvements by exposing more parallelism using YUV and frame-based parallel decoding. We also present platform optimizations based on the use of SIMD functions and cache efficient FIFOs. Results show an average acceleration factor of 5.8 in the decoding framerate over the reference architecture.

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  1. Orcc is available at http://orcc.sf.net

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Acknowledgments

This work is done as part of 4EVER, a French national project with support from Europe (FEDER), French Ministry of Industry, from French Regions of Brittany, Ile-de-France and Provence-Alpes-Côte-d’Azur, from Competitivity clusters Images & Reseaux (Brittany), from Cap Digital (Ile-de-France), and from Solutions Communicantes Securisées (Provence-Alpes-Côte-d’Azur).

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Authors and Affiliations

  1. IETR/INSA Rennes, CNRS UMR 6164, UEB, 20, Av. des Buttes de Coesmes, 35708, Rennes, France

    Khaled Jerbi, Hervé Yviquel, Alexandre Sanchez & Mickaël Raulet

  2. Microelectronic Systems Lab, EPFL Lausanne, EPFL CH-1015, Lausanne, Switzerland

    Daniele Renzi, Damien De Saint Jorre, Claudio Alberti & Marco Mattavelli

Authors
  1. Khaled Jerbi
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  2. Hervé Yviquel
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  3. Alexandre Sanchez
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  4. Daniele Renzi
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  5. Damien De Saint Jorre
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  6. Claudio Alberti
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  7. Marco Mattavelli
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  8. Mickaël Raulet
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Correspondence to Khaled Jerbi.

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Jerbi, K., Yviquel, H., Sanchez, A. et al. On the Development and Optimization of HEVC Video Decoders Using High-Level Dataflow Modeling. J Sign Process Syst 87, 127–138 (2017). https://doi.org/10.1007/s11265-016-1113-x

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  • DOI: https://doi.org/10.1007/s11265-016-1113-x

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