Abstract
Fractional Motion Estimation (FME) in high-definition H.264 presents a significant design challenge in terms of memory bandwidth, latency and area cost as there are various modes and complex mode decision flow, which require over 45% of the computation complexity in the H.264 encoding process. In this paper, a new high-performance VLSI architecture for Fractional Motion Estimation (FME) in H.264/AVC based on the full-search algorithm is presented. This architecture is made up of three different pipeline processors to establish a trade-off between processing time and hardware utilization. The computing scheme based on a 4-pixel interpolation unit with a 10-pixel input bandwidth is capable of processing a macroblock (MB) in 870 clock cycles. The final VLSI implementation only requires 11.4 k gates and 4.4kBytes of RAM in a standard 180 nm CMOS technology operating at 290 MHz. Our design generates the residual image and the best MVs and mode in a high throughput and low area cost architecture while achieving enough processing capacity for 1080HD (1920 × 1088@30fps) real-time video streams.
Similar content being viewed by others
References
Ostermann, J., Bormans, J., List, P., Marpe, D., Narroschke, M., Pereira, F., et al. (2004). Video coding with H.264/AVC: tools, performance, and complexity. IEEE Circuits and Systems Magazine, 4(1), 7–28. First Quarter.
Wiegand, T., Sullivan, G. J., Bjontegaard, G., & Luthra, A. (2003). Overview of H.264/AVC video coding standard. IEEE Transactions on Circuits and Systems for Video Technology, 13(7), 560–576.
ITU-T Rec. H.264/ISO/IEC 11496-10 (2003). Advanced Video Coding. Final Committee Draft, Document JVTG050.
Online document. http://iphome.hhi.de/suehring/tml/. Accessed 17 September 2009.
Yap, S. Y., & McCanny, J. V. (1989). A VLSI architecture for variable block size video motion estimation. IEEE Transactions on Circuits and Systems for Video Technology, 36(2), 1301–1308.
Komarek, T., & Pirsh, P. (2006). Array architectures for block matching algorithms. IEEE Transactions on Circuits and Systems for Video Technology, 16(7), 876–883.
Jong, H. M., Chen, L. G., & Chiueh, T. D. (1994). Parallel architecture for 3-step hierarchical search block-matching algorithm. IEEE Transactions on Circuits and Systems for Video Technology, 4(4), 407–416.
Zhu, C., Lin, X., & Chau, L. P. (2002). Hexagon-based search pattern for fast block motion estimation. IEEE Transactions on Circuits and Systems for Video Technology, 12(5), 349–355.
Zhu, C., & Ma, K. K. (2000). A new diamond search algorithm, for fast block matching motion estimation. IEEE Transactions on Image Processing, 9(2), 287–290.
Chen, T. C., Chen, Y. H., Tsai, S. F., Chien, S. I., & Chen, L. G. (2007). Fast algorithm and architecture design of low-power integer motion estimation for H.264/AVC. IEEE Transactions on Circuits and Systems for Video Technology, 17(5), 568–577.
Li, D. X., & Zhang, M. (2007). Architecture design for H.264/AVC integer motion estimation with minimum memory bandwidth. IEEE Transactions on Consumer Electronics, 53(3), 1053–1060.
Zhenyu, W., Baochen, J., Xudong, Z., & Yu, C. (2004). A new full-pixel and sub-pixel motion vector search algorithm for fast block-matching motion estimation in H.264. Proceedings of the Third International Conference on Image and Graphics, 345–348.
La, B., Eom, M., & Choe, Y. (2007). Fast sub-pixel search control by using neighbour motion vector in H.264. 9th International Conference on Advanced Communication Technology, 1, 62–65.
Hyun, C. J., Kim, S. D., & Sunwoo, M. H. (2006). Efficient memory reuse and sub-pixel interpolation algorithms for ME/MC of H.264/AVC. IEEE Workshop on Signal Processing Systems Design and Implementation, 377–382. October.
Song, Y., Ma, Y., Liu, Z., Ikenaga, T., & Goto, S. (2008). Hardware-oriented direction-based fast fractional motion estimation algorithm in H.264/AVC. IEEE International Conference on Multimedia and Expo, 1009–1012, June.
Chen, T. C., Huang, Y. W., & Chen, L. G. (2004). Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC. IEEE International Conference on Acoustics, Speech, and Signal Processing, 5, 9–12.
Yang, C., Goto, S., Ikenaga, T. (2006). High performance VLSI architecture of fractional motion estimation in H.264 for HDTV. IEEE International Symposium on Circuits and Systems, 2605–2608.
Song, Y., Liu, Z., Goto, S., & Ikenaga, T. (2005). A VLSI architecture for Motion compensation interpolation in H.264/AVC. 6th International Conference on ASIC, 279–282. October.
Wu, C. L., Kao, C. Y., & Lin, Y. L. (2008). A high performance three-engine architecture for H.264/AVC fractional motion estimation. IEEE International Conference on Multimedia and Expo, 133–136.
Wang, Y. J., Cheng, C. C., & Chang, T. S. (2007). A fast algorithm and its VLSI architecture for fractional motion estimation for H.264/MPEG-4 AVC video coding. IEEE Transactions on Circuits and Systems for Video Technology, 17(5), 578–583.
Lin, Y. K., Lin, C. C., Kuo, T. Y., & Chang, T. S. (2008). A hardware-efficient H.264/AVC motion-estimation design for high-definition video. IEEE Transactions on Circuits and Systems, 55(6), 1526–1535.
Yalcin, S., & Hamzaoglu, I. (2006). A high performance hardware architecture for half-pixel accurate H.264 motion estimation. IFIP International Conference on Very Large Scale Integration, 63–67. October.
Rahman, C. A. & Badawy, W. (2005). A quarter pel full search block motion estimation architecture for H.264/AVC. IEEE International Conference on Multimedia and Expo, 414–417. July.
Chen, T. C., Chien, S. Y., Huang, Y. W., Tsai, C. H., Chen, C. Y., Chen, T. W., et al. (2006). Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder. IEEE Transactions on Circuits and Systems for Video Technology, 16(6), 673–688.
Huang, Y. W., Chen, T. C., Tsai, C. H., Chen, C. Y., Chen, T. W., Chen, C. S., et al. (2005). A 1.3TOPS H.264/AVC Single-Chip Encoder for HDTV Applications. ISSCC Digest of Technical Paper, 128–129. February.
Sihvo, T., & Niittylahti, J. (2005). H.264/AVC interpolation optimization. IEEE Workshop on Signal Processing Systems Design and Implementation, 307–312. November.
Vanne, J., Ahn, E., Hämäläinen, T. D., & Kuusilinna, K. (2006). A high-performance sum of absolute difference implementation for motion estimation. IEEE Transactions on Circuits and Systems for Video Technology, 16(7), 876–883.
Acknowledgment
We wish to acknowledge the Spanish Ministry of Education and Science for the financial help TEC2006-12438/TCM received to support this work.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Ruiz, G.A., Michell, J.A. An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV. J Sign Process Syst 62, 443–457 (2011). https://doi.org/10.1007/s11265-010-0475-8
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11265-010-0475-8