Skip to main content
Log in

Abstract

Embedded digital signal processors for software defined radio have stringent design constraints including high computational bandwidth, low power consumption, and low interrupt latency. Furthermore, due to rapidly evolving communication standards with increasing code complexity, these processors must be compiler-friendly, so that code for them can quickly be developed in a high-level language. In this paper, we present the design of the Sandblaster Processor, a low-power multithreaded digital signal processor for software defined radio. The processor uses a unique combination of token triggered threading, powerful compound instructions, and SIMD vector operations to provide real-time baseband processing capabilities with very low power consumption. We describe the processor’s architecture and microarchitecture, along with various techniques for achieving high performance and low power dissipation. We also describe the processor’s programming environment and the SB3010 platform, a complete system-on-chip solution for software defined radio. Using a super-computer class vectorizing compiler, the SB3010 achieves real-time performance in software on a variety of communication protocols including 802.11b, GPS, AM/FM radio, Bluetooth, GPRS, and WCDMA. In addition to providing a programmable platform for SDR, the processor also provides efficient support for a wide variety of digital signal processing and multimedia applications.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. J.P. Shen and M. Lipasti, “Modern Processor Design: Fundamentals of Superscalar Processors,” New York, McGraw-Hill Book Company, 2005.

    Google Scholar 

  2. D.M. Tullsen, S.J. Eggers, H.M. Levy, “Simultaneous Multithreading: Maximizing on-chip Parallelism,” Proceedings of the International Symposium on Computer Architecture, 1995, pp. 392–403.

  3. P. Lapsley, J. Bier, A. Shoham, and E.A. Lee, “DSP Processor Fundamentals: Architectures and Features,” New York, IEEE Press, 1997.

    Book  MATH  Google Scholar 

  4. J.T.J. van Eijndhoven, F.W. Sijstermans, K.A. Vissers, E.J.D. Pol, M.I.A. Tromp, P. Struik, R.H.J. Bloks, P. van der Wolf, A.D. Pimentel, and H.P.E. Vranken, “TriMedia CPU64 Architecture,” Proceedings of the International Conference on Computer Design, 1999, pp. 586–592.

  5. O. Wolf and J. Bier, “StarCore Launches First Architecture,” Microprocessor Report, vol. 12, 1998, pp. 1–4.

    Google Scholar 

  6. J. Fridman and Z. Greenfield, “The TigerSHARC DSP Architecture,” IEEE Micro, vol. 20, 2000, pp. 66–76.

    Article  Google Scholar 

  7. N. Seshan, “High VelociTI Processing: Texas Instruments VLIW DSP Architecture,” IEEE Signal Processing Magazine, vol. 15, 1998, pp. 86–101, 117.

  8. R.K. Kolagotla, J. Fridman, B.C. Aldrich, M.M. Hoffman, W.C. Anderson, M.S. Allen, D.B. Witt, R.R. Dunton, and L.A. Booth, Jr., “High Performance Dual-MAC DSP Architecture,” IEEE Signal Processing Magazine, vol. 19, 2002, pp. 42–53.

    Article  Google Scholar 

  9. J. Glossner, D. Iancu, J. Lu, E. Hokenek, and M. Moudgill, “A Software Defined Communications Baseband Design,” IEEE Communications Magazine, vol. 41, 2003, pp. 120–128.

    Article  Google Scholar 

  10. A.M. Eltawil and B. Daneshrad, “A Low-power DS-CDMA RAKE Receiver Utilizing Resource Allocation Techniques,” IEEE Journal of Solid-State Circuits, vol. 39, 2004, pp. 1321–1330.

    Article  Google Scholar 

  11. M. Mehta, N. Drew, G. Vardoulias, N. Greco, and C. Niedermeier, “Reconfigurable Terminals: An Overview of Architectural Solutions,” IEEE Communications Magazine, vol. 39, 2001, pp. 146–155.

    Article  Google Scholar 

  12. M.J. Schulte, J. Glossner, S. Mamidi, M. Moudgill, and S. Vassiliadis, “A Low-Power Multithreaded Processor for Baseband Communication Systems,” in Embedded Processor Design Challenges: Systems, Architectures, Modelling, and Simulation, Lecture Notes in Computer Science, Norwell, MA, Springer, vol. 3133, 2004, pp. 393–402.

  13. J. Glossner, K. Chirca, M.J. Schulte, H. Wang, N. Nasimzada, D. Har, S. Wang, A.J. Hoane, Jr., G. Nacer, M. Moudgill, and S. Vassiliadis, “Sandbridge Sandblaster Low Power DSP,” in Proceedings of the IEEE Custom Integrated Circuits Conference, 2004, pp. 575–581.

  14. J. Glossner, E. Hokenek, and M. Moudgill, “The Sandbridge Sandblaster Communications Processor,” Software Defined Radio: Baseband Technology for 3G Handsets and Basestations, West Sussex, England, John Wiley & Sons, SDR Series, vol. 5, 2004, pp. 129–157.

  15. J. Glossner, T. Raja, E. Hokenek, and M. Moudgill, “A Multithreaded Processor Architecture for SDR,” Proceedings of the Korean Institute of Communication Sciences, vol. 19, 2002, pp. 70–84.

    Google Scholar 

  16. J. Glossner, M. Schulte, and S. Vassiliadis, “A Java-Enabled DSP,” Embedded Processor Design Challenges, Systems, Architectures, Modeling, and Simulation (SAMOS) Lecture Notes in Computer Science, vol. 2268, Berlin, Springer-Verlag, 2002, pp. 307–325.

  17. J. Glossner, M. Moudgill, D. Iancu, G. Nacer, S. Jinturkar, S. Stanley, M. Samori, T. Raja, and M. J. Schulte, “The Sandbridge Sandblaster Convergence Platform,” pp. 1–21, 2005. Available from: http://www.sandbridgetech.com/documents/sandbridge_white_paper_2005.pdf.

  18. J.P. Wittenburg, P. Pirsch, and G. Meyer, “A Multithreaded Architecture Approach to Parallel DSPs for High Performance Image Processing Applications,” Proceedings of the IEEE Workshop on Signal Processing Systems, 1999, pp. 241–250.

  19. H. Oehring, U. Sigmund, and T. Ungerer, “MPEG-2 Video Decompression on Simultaneous Multithreaded Multimedia Processors,” Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 1999, pp. 11–16.

  20. Y.-K. Chen, E. Debes, R. Lienhart, M. Holliman, and M. Yeung, “Evaluating and Improving Performance of Multimedia Applications on Simultaneous Multithreading,” Proceedings of the Ninth International Conference on Parallel and Distributed Systems, 2002, pp. 529–534.

  21. S. Kaxiras, G. Narlikar, A.D. Berenbaum, and Z. Hu, “Comparing Power Consumption of an SMT and a CMP DSP for Mobile Phone Workloads,” Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, 2001, pp. 211–220.

  22. T. Ungerer, B. Robie, and J. Šilc, “A Survey of Processors with Explicit Multithreading,” ACM Computing Surveys, vol. 35, 2003, pp. 29–63.

    Article  Google Scholar 

  23. B.J. Smith, “The Architecture of HEP,” Parallel MIMD Computation: HEP Supercomputer and Its Applications Cambridge, MA, MIT Press, 1985, pp. 41–55.

    Google Scholar 

  24. R. Alveston, D. Callahan, D. Cummings, R. Koblenz, B. Porterfield, and B.J. Smith, “The Tera Computer System,” Proceedings of the 4th International Conference on Supercomputing, 1990, pp. 1–6.

  25. A. Agarwal, J. Kubiatowicz, R. Kranz, B.H. Lim, D. Yeong, G.D’Souza, and M. Parkin, “Sparcle: An Evolutionary Processor Design for Large-Scale Multiprocessors,” IEEE Micro, vol. 13, 1993, pp. 48–61.

    Article  Google Scholar 

  26. U. Brinkschulte, C. Krakowski, J. Kreuzinger, and T. Ungerer, “A Multithreaded Java Microcontroller for Thread-oriented Realtime Event-handling,” Proceedings of the International Conference on Parallel Architectures and Compilation, 1999, pp. 34–39.

  27. D.M. Tullsen, S.J. Eggers, S.J. Emers, H.M. Levy, J.L. Lo, and R.L. Stamm, “Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor,” Proceedings of the 23rd Annual International Symposium on Computer Architecture, 1996, pp. 191–202.

  28. J.S. Seng, D.M. Tullsen, and G.Z.N. Cai, “Power-sensitive Multithreaded Architecture,” Proceedings of the International Conference on Computer Design, 2000, pp. 199–206.

  29. J.W. Haskins, Jr., K.R. Hirst, and K. Skadron, “Inexpensive Throughput Enhancement in Small-scale Embedded Microprocessors with Block Multithreading: Extensions, Characterization, and Tradeoffs,” Proceedings of the IEEE International Conference on Performance, Computing, and Communications, 2001, pp. 319–328.

  30. W. El-Kharashi, F. ElGuibaly, and K.F. Li, “Multithreaded Processors: The Upcoming Generation for Multimedia Chips,” Proceedings of the IEEE Symposium on Advances in Digital Filtering and Signal Processing, 1998, pp. 111–115.

  31. F.J. Cazorla, A. Ramirez, M. Valero, P.M.W. Knijnenburg, R. Sakellariou, and E. Fernandez, “QoS for High-performance SMT Processors in Embedded Systems,” IEEE Micro, vol. 24, 2004, pp. 24–31.

    Article  Google Scholar 

  32. J. Sebot and N. Drach, “SIMD Extensions: Reducing Power Consumption on a Superscalar Processor for Multimedia Applications,” Cool Chips, vol. IV, April 2001.

  33. R.B. Lee, “Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures,” Proceedings of the IEEE 11th International Conference on Application-Specific Systems, Architectures and Processor, 2000, pp. 3–14.

  34. M.J. Schulte, P.I. Balzola, J. Ruan, and J. Glossner, “Parallel Saturating Multioperand Adders,” Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, 2000, pp. 172–179.

  35. P. Balzola, M. Schulte, J. Ruan, J. Glossner, and E. Hokenek, “Design Alternatives for Parallel Saturating Multioperand Adders,” Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors, 2001, pp. 172–177.

  36. T. Boudreau, J. Glick, S. Greene, J. Woehr, and V. Spurlin, “NetBeans: The Definitive Guide,” Sebastopol, CA, O’Reilly & Associates, 2002.

  37. K.W. Leary and W. Waddington, “DSP/C: A Standard High Level Language for DSP and Numeric Processing,” Proceedings of the International Conference on Acoustics, Speech and Signal Processing, IEEE, 1990, pp. 1065–1068.

  38. D. Batten, S. Jinturkar, J. Glossner, M. Schulte, and P. D’Arcy, “A New Approach to DSP Intrinsic Functions,” Proceedings of the Hawaii International Conference on System Sciences, 2000, pp. 2892–2901.

  39. S. Jinturkar, J. Glossner, V. Kotlyar, and M. Moudgill, “The Sandblaster Automatic Multithreaded Vectorizing Compiler,” Proceedings of the 2004 Global Signal Processing Expo (GSPx) and International Signal Processing Conference 2004.

  40. V. Kotlyar and M. Moudgill, “Detecting Overflow Detection,” Proceedings of the 2004 CODES+ISSS International Conference on Hardware/Software Codesign and System Synthesis, 2004, pp. 36–41.

  41. J. Glossner, S. Dorward, S. Jinturkar, M. Moudgill, E. Hokenek, M. Schulte, and S. Vassiliadis, “Sandbridge Software Tools,” Proceedings of the 3rd Annual Systems, Architectures, Modelling, and Simulation (SAMOS) Conference, Samos, Greece, 2003, pp. 142–148.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Michael Schulte.

Additional information

Michael Schulte received a B.S. degree in Electrical Engineering from the University of Wisconsin-Madison in 1991, and M.S. and Ph.D. degrees in Electrical Engineering from the University of Texas at Austin in 1992 and 1996, respectively. From 1996 to 2002, he was an assistant and associate professor at Lehigh University, where he directed the Computer Architecture and Arithmetic Research Laboratory. He is currently an assistant professor at the University of Wisconsin-Madison, where he leads the Madison Embedded Systems and Architectures Group. His research interests include high-performance embedded processors, computer architecture, domain-specific systems, computer arithmetic, and wireless systems. He is a senior member of the IEEE and the IEEE Computer Society, and an associate editor for the IEEE Transactions on Computers and the Journal of VLSI Signal Processing.

John Glossner is CTO & Executive Vice President at Sandbridge Technologies. Prior to co-founding Sandbridge, John managed the Advanced DSP Technology group, Broadband Transmission Systems group, and was Access Aggregation Business Development manager at IBM’s T.J. Watson Research Center. Prior to IBM, John managed the software effort in Lucent/Motorola’s Starcore DSP design center. John received a Ph.D. in Computer Architecture from TU Delft in the Netherlands for his work on a Multithreaded Java processor with DSP capability. He also received an M.S. degree in Engineering Management and an M.S.E.E. from NTU. John also holds a B.S.E.E. degree from Penn State. John has more than 60 publications and 12 issued patents.

Dr. Sanjay Jinturkar is the Director of Software at Sandbridge and manages the systems software and communications software groups. Previously, he managed the software tools group at StarCore. He has a Ph.D in Computer Science from University of Virginia and holds 20 publications and 4 patents.

Mayan Moudgill obtained a Ph.D. in Computer Science from Cornell University in 1994, after which he joined IBM at the Thomas J. Watson Research Center. He worked on a variety of computer architecture and compiler related projects, including the VLIW research compiler, Linux ports for the 40x series embedded processors and simulators for the Power 4. In 2001, he co-founded Sandbridge Technologies, a start-up that is developing digital signal processors targeted at 3G wireless phones.

Suman Mamidi is a graduate student in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. He received his M.S. degree from the University of Wisconsin-Madison in December, 2003 and is currently working towards his PhD. His research interests include low-power processors, hardware accelerators, multithreaded processors, reconfigurable hardware, and embedded systems.

Stamatis Vassiliadis was born in Manolates, Samos, Greece, in 1951. He is currently a Chair Professor in the Electrical Engineering, Mathematics, and Computer Science (EEMCS) department of Delft University of Technology (TU Delft), The Netherlands. He previously served in the Electrical and Computer Engineering faculties of Cornell University, Ithaca, NY and the State University of New York (S.U.N.Y.), Binghamton, NY. For a decade, he worked with IBM, where he was involved in a number of advanced research and development projects. He received numerous awards for his work, including 24 publication awards, 15 invention awards, and an outstanding innovation award for engineering/scientific hardware design. His 73 USA patents rank him as the top all time IBM inventor. Dr. Vassiliadis is an ACM fellow, an IEEE fellow and a member of the Royal Netherlands Academy of Arts and Sciences (KNAW).

Rights and permissions

Reprints and permissions

About this article

Cite this article

Schulte, M., Glossner, J., Jinturkar, S. et al. A Low-Power Multithreaded Processor for Software Defined Radio. J VLSI Sign Process Syst Sign Image Video Technol 43, 143–159 (2006). https://doi.org/10.1007/s11265-006-7267-1

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-006-7267-1

Keywords

Navigation