Abstract
Multicore technology has the potential for drastically increasing productivity of embedded real-time computing. However, joint use of hardware, e.g., caches, memory banks and on-chip buses makes the integration of multiple real-time applications into a single system difficult: resource accesses are exclusive and need to be sequenced. Moreover, resource access schemes of modern off-the-shelf multicore chips are commonly optimized for the average-case, rather than being timing predictable. Real-time analysis for such architectures is complex, as execution times depend on the deployed hardware, as well as on the software executing on other cores. This will ask for significant abstractions in the timing analysis, where the resulting pessimism will lead to over-provisioned system designs and a lowered productivity as the number of applications to be put together into a single architecture needs to be decreased. In response to this, (a) we present a formal approach for bounding the worst-case response time of concurrently executing real-time tasks under resource contention and almost arbitrarily complex resource arbitration policies, with a focus on main memory as shared resource, (b) we present a simulation framework which allows for detailed modeling and empirical evaluation of modern multicore platforms and applications running on top of them, and (c) we present experiments to demonstrate the advantages and disadvantages of the presented methodologies and compare their accuracy. For limiting non-determinism inherent to the occurrence of cache misses, we particularly take advantage from the predictable execution model as discussed in recent works.
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Notes
In Pellizzoni et al. (2011), the term predictable interval is used with the same meaning as superblock.
Provided that the system is schedulable, i.e., execution of a superblock sequence always finishes within the current processing cycle.
Instead of a single staircase curve, \(\alpha ^{st}\) can also be composed from sets of staircase curves put together via nested maximum and minimum operations (Lampka et al. 2010; Perathoner et al. 2011). This allows to model more complex curves, however, substantially adds to the complexity of the model checking problem to be solved when determining the WCRT of the CUA.
Case studies with FlexRay are omitted here for brevity, but can be found in Giannopoulou et al. (2012).
The authors of Lundqvist and Stenstrom (1999) propose a method which avoids timing anomalies due to out-of-order (micro)-instruction execution. It is empirical shown that such efforts might not utterly compromise the performance of the original software.
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Acknowledgments
We thank the anonymous reviewers for the valueable remarks and the resulting improvements of the article. This work has received funding from the European Union Seventh Framework Programme (FP7/2007-2013) project CERTAINTY under Grant Agreement Number 288175 and from the NSERC under Discovery Grant 402369-2011. Any opinions, findings, and conclusions or recommendations expressed in this publication are those of the authors and do not necessarily reflect the views of the sponsors.
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Lampka, K., Giannopoulou, G., Pellizzoni, R. et al. A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets. Real-Time Syst 50, 736–773 (2014). https://doi.org/10.1007/s11241-014-9211-y
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DOI: https://doi.org/10.1007/s11241-014-9211-y