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Latency-aware DVFS for efficient power state transitions on many-core architectures

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Abstract

Energy efficiency is quickly becoming a first-class design constraint in high-performance computing (HPC). We need more efficient power management solutions to save energy costs and carbon footprint of HPC systems. Dynamic voltage and frequency scaling (DVFS) is a commonly used power management technique for making a trade-off between power consumption and system performance according to the time-varying program behavior. However, prior work on DVFS seldom takes into account the voltage and frequency scaling latencies, which we found to be a crucial factor determining the efficiency of the power management scheme. Frequent power state transitions without latency awareness can make a real impact on the execution performance of applications. The design of multiple voltage domains in some many-core architectures has made the effect of DVFS latencies even more significant. These concerns lead us to propose a new latency-aware DVFS scheme to adjust the optimal power state more accurately. Our main idea is to analyze the latency characteristics in depth and design a novel profile-guided DVFS solution which exploits the varying execution patterns of the parallel program to avoid excessive power state transitions. We implement the solution into a power management library for use by shared-memory parallel applications. Experimental evaluation on the Intel SCC many-core platform shows significant improvement in power efficiency after using our scheme. Compared with a latency-unaware approach, we achieve 24.0 % extra energy saving, 31.3 % more reduction in the energy–delay product and 15.2 % less overhead in execution time in the average case for various benchmarks. Our algorithm is also proved to outperform a prior DVFS approach attempted to mitigate the latency effects.

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Notes

  1. Including external cooling, the system would draw an aggregate power of 24 megawatts.

  2. In 2013, average annual residential electricity consumptions per capita in China and US are 498.6 kWh and 4,327.6 kWh, respectively. Detailed calculations and sources: Electricity consumption by China’s urban and rural residents (\(E_\mathrm{china}\)) is \(6,793 \times 10^8\) kWh [25]. China’s population (\(P_\mathrm{china}\)) as of September, 2013 is 1,362,391,579 [45]. Dividing \(E_\mathrm{china}\) by \(P_\mathrm{china}\) gives 498.6 kWh. Electricity usage per household in US (\(E_\mathrm{us}\)) in 2013 is 10,819 kWh [7]. Average household size in US (\(P_\mathrm{us}\)) (or in most wealthy countries) is close to 2.5 persons [44]. Dividing \(E_\mathrm{us}\) by \(P_\mathrm{us}\) gives 4,327.6  kWh.

  3. Our estimation is done as follows: Tianhe-2 is using Xeon E5 2692v2 and Xeon Phi 31S1P (with 125 and 270 W TDPs). Assume their average power consumptions are 90 and 165 W (reference [20]), respectively. 90 W \(\times \) 32,000 + 165 W \(\times \) 48,000 = 10,800 kW. Divided by 17,808 kW gives 60.65 %.

  4. For practical safety, we apply a slightly higher voltage than the theoretical least voltage, hence there is a small margin between the theoretical safe boundary curve and the least-voltage operating points for each frequency in Fig. 1.

  5. We are aware of a recent compiler-based study [48] showing diminishing returns from DVFS by their analysis based on a high-level model. They argue that the reduction of dynamic power using DVFS is trivial compared with the total system power, considering the performance degradation due to DVFS, and therefore a “race to sleep” approach is indeed more energy efficient than using DVFS. However, this is true only for compute-bound workloads. We observe two latest phenomena that are against the conclusion of their analysis. First, for the state-of-the-art supercomputers such as Tianhe-2, the many-core (co)processors have dominated the entire system power by up to 60 %. Second, it is increasingly important to support the class of data-intensive HPC or multi-tenant cloud computing workloads nowadays. Such relatively memory-bound or I/O-bound workloads expose rich opportunity for DVFS to reap energy saving. So, DVFS is still an effective technique to achieve performance–energy trade-off as we have experimentally confirmed.

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Acknowledgments

This work is supported by Hong Kong RGC Grant HKU 716712E, National Basic Research Program of China (973) (No. 2014CB340303) and National Natural Science Foundation of China (No. 61303264, 61202482). Special thanks go to Intel China Center of Parallel Computing (ICCPC) and Beijing Soft Tech Technologies Co., Ltd. for providing us their support services of the SCC platform in their Wuxi data centers.

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  1. National Key Laboratory of Parallel and Distributed Processing, College of Computer, National University of Defense Technology, Changsha, China

    Zhiquan Lai & Jinshu Su

  2. Department of Computer Science, The University of Hong Kong, Hong Kong, China

    King Tin Lam & Cho-Li Wang

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  1. Zhiquan Lai
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Correspondence to Zhiquan Lai.

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Lai, Z., Lam, K.T., Wang, CL. et al. Latency-aware DVFS for efficient power state transitions on many-core architectures. J Supercomput 71, 2720–2747 (2015). https://doi.org/10.1007/s11227-015-1415-y

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