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A methodology for speeding up matrix vector multiplication for single/multi-core architectures

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Abstract

In this paper, a new methodology for computing the Dense Matrix Vector Multiplication, for both embedded (processors without SIMD unit) and general purpose processors (single and multi-core processors, with SIMD unit), is presented. This methodology achieves higher execution speed than ATLAS state-of-the-art library (speedup from 1.2 up to 1.45). This is achieved by fully exploiting the combination of the software (e.g., data reuse) and hardware parameters (e.g., data cache associativity) which are considered simultaneously as one problem and not separately, giving a smaller search space and high-quality solutions. The proposed methodology produces a different schedule for different values of the (i) number of the levels of data cache; (ii) data cache sizes; (iii) data cache associativities; (iv) data cache and main memory latencies; (v) data array layout of the matrix and (vi) number of cores.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Patras, Patras, Greece

    Vasilios Kelefouras, Elissavet Papadima & Costas Goutis

  2. Education and Research Department in Computer science and Electrical Engineering, University of Rennes 1-IRISA/INRIA, Rennes, France

    Angeliki Kritikakou

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  1. Vasilios Kelefouras
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  2. Angeliki Kritikakou
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  3. Elissavet Papadima
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  4. Costas Goutis
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Correspondence to Vasilios Kelefouras.

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Kelefouras, V., Kritikakou, A., Papadima, E. et al. A methodology for speeding up matrix vector multiplication for single/multi-core architectures. J Supercomput 71, 2644–2667 (2015). https://doi.org/10.1007/s11227-015-1409-9

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