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Analysis of a temperature-dependent delay optimization model for GNR interconnects using a wire sizing method

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Abstract

A temperature-dependent delay optimization model for a multilayered graphene nanoribbon (MLGNR) with top contact (TC-GNR), side contact (SC-GNR), and Cu-based nano-interconnects using a wire sizing method was applied to determine the delay for different interconnects widths (11 nm, 16 nm, and 22 nm) and lengths (10 μm, 50 μm, and 100 μm), being the first such model for TC-GNR, SC-GNR, and Cu interconnects applied at three different chip operating temperatures (233 K, 300 K, and 378 K). The results reveal that the SC-GNR requires ~ 3–6× and ~ 2–3× fewer repeaters w.r.t. the TC-GNR or Cu interconnect, and that the SC-GNR and Cu interconnects can achieve ~ 4–5× and ~ 2–2.5× reduction in repeater dimension compared with the TC-GNR interconnect. Meanwhile, the SC-GNR interconnect can achieve 73× less propagation delay w.r.t. the TC-GNR interconnect for interconnect width of 22 nm, interconnect length of 10 μm, and two different chip operating temperatures of 233 K and 300 K. Similarly, the Cu interconnect can achieve 6× less propagation delay w.r.t. the TC-GNR interconnect at interconnect width of 22 nm and 16 nm, interconnect length of 10 μm, and 300 K.

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Funding

SMDP-C2SD, DeitY, MCIT, India.

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Authors and Affiliations

  1. School of VLSI Technology, Indian Institute of Engineering Science and Technology, Shibpur, India

    Sandip Bhattacharya, Subhajit Das, Arnab Mukhopadhyay & Hafizur Rahaman

  2. Department of Electronics and Communication Engineering, Assam University, Silchar, India

    Debaprasad Das

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  1. Sandip Bhattacharya
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  2. Subhajit Das
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  3. Arnab Mukhopadhyay
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  4. Debaprasad Das
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  5. Hafizur Rahaman
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Correspondence to Sandip Bhattacharya.

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Bhattacharya, S., Das, S., Mukhopadhyay, A. et al. Analysis of a temperature-dependent delay optimization model for GNR interconnects using a wire sizing method. J Comput Electron 17, 1536–1548 (2018). https://doi.org/10.1007/s10825-018-1251-4

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