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Gate and drain SEU sensitivity of sub-20-nm FinFET- and Junctionless FinFET-based 6T-SRAM circuits by 3D TCAD simulation

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Abstract

Scaling of metal–oxide–semiconductor field-effect transistors (MOSFETs) to below a few tens of nanometer has failed to make significant improvements. FinFETs were introduced to replace MOS devices in circuits, offering good performance improvement in the nanoscale regime. Memories occupy a major portion of chip area. Their reliability is a primary concern in harsh environments such as cosmic radiation. Also, in the nanoscale regime, reliability proves to be challenging. We present herein FinFET- and junctionless FinFET-based 6T-static random-access memories (SRAMs) for the 16-nm technology node. In the literature so far, either drain or gate strike has been considered. In this work, we studied irradiation in both the drain and the gate region. The FinFET-based 6T-SRAM showed higher hardness to single-event upset (SEU) radiation in both regions compared to junctionless FinFET-based 6T-SRAM.

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  1. Department of Micro and Nanoelectronics, School of Electronics Engineering, VIT University, Vellore, 632014, India

    S. Nilamani & V. N. Ramakrishnan

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  1. S. Nilamani
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  2. V. N. Ramakrishnan
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Correspondence to V. N. Ramakrishnan.

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Nilamani, S., Ramakrishnan, V.N. Gate and drain SEU sensitivity of sub-20-nm FinFET- and Junctionless FinFET-based 6T-SRAM circuits by 3D TCAD simulation. J Comput Electron 16, 74–82 (2017). https://doi.org/10.1007/s10825-016-0950-y

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  • DOI: https://doi.org/10.1007/s10825-016-0950-y

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