Abstract
With the development of more compact and powerful methods of designing a digital logic on a silicon chip, most of the signal processing is being implemented in the digital domain. The implementation of an efficient reconfigurable digital decimation filter is presented in the work. In this paper we focuses with the implementation and design of a decimation filter which is used for hearing aid applications. We design decimation filter with the help of the canonic signed digit (CSD) representation. In decimation filter the cascaded integrated comb filter is designed using without multiplier less. The half band and corrector filters are designed using CSD. The decimation filter has been implemented on Xilinx FPGA using Virtex-2 technology and number of slices ,number of LUTs and number of registers are reported and also proposed design is implemented in synopsis design compiler for ASIC implementation and calculated area, power and delay. The resulting architecture is hardware efficient and consumes less power compared to conventional decimation filters. Compared to the normal decimation filter architecture, the proposed decimation filter architecture has less hardware saving of 60% and in addition, it decreases the power consumption of 80%, respectively and the proposed architecture is well suited for decimation filters of the hearing aids.
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Niveditha, V.R., Palaniappan, S., Naresh, K. et al. High speed low area decimation filter for hearing aid application. Int J Speech Technol 25, 633–639 (2022). https://doi.org/10.1007/s10772-021-09857-5
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DOI: https://doi.org/10.1007/s10772-021-09857-5