Abstract
We propose a scalable, low-noise imager architecture for terahertz recordings that helps to build large-scale integrated arrays from any field-effect transistor (FET)- or HEMT-based terahertz detector. It enhances the signal-to-noise ratio (SNR) by inherently enabling complex sampling schemes. The distinguishing feature of the architecture is the serially connected detectors with electronically controllable photoresponse. We show that this architecture facilitate room temperature imaging by decreasing the low-noise amplifier (LNA) noise to one-sixteenth of a non-serial sensor while also reducing the number of multiplexed signals in the same proportion. The serially coupled architecture can be combined with the existing read-out circuit organizations to create high-resolution, coarse-grain sensor arrays. Besides, it adds the capability to suppress overall noise with increasing array size. The theoretical considerations are proven on a 4 by 4 detector array manufactured on 180 nm feature sized standard CMOS technology. The detector array is integrated with a low-noise AC-coupled amplifier of 40 dB gain and has a resonant peak at 460 GHz with 200 kV/W overall sensitivity.
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Acknowledgments
The work is supported by the Hungarian Scientific Research Fund—National Office for Research and Technology OTKA-NTKH CNK-77564 project. In addition, the support of the grants TÁMOP-4.2.1.B-11/2/KMR-2011-0002 and TÁMOP-4.2.2/B-10/1-2010-0014 is gratefully acknowledged as well. We also thank the work of Zsolt Benedek in the layout design of the detector chip.
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Péter Földesy holds a PhD, Budapest University of Technology and Economics.
Ákos Zarándy holds a DSc, Hungarian Academy of Sciences.
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Gergelyi, D., Földesy, P. & Zarándy, Á. Scalable, Low-Noise Architecture for Integrated Terahertz Imagers. J Infrared Milli Terahz Waves 36, 520–536 (2015). https://doi.org/10.1007/s10762-015-0153-9
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DOI: https://doi.org/10.1007/s10762-015-0153-9