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Process evaluation in FinFET based 7T SRAM cell

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Abstract

The main aim of device scaling or usage of different technology is to reduce power. The major problem with technology scaling is power dissipation and stability of the device. SRAM is an integral part of any memory, different topologies are proposed in SRAM to address the problem of power dissipation and stability in nanometer technologies. FinFET based devices have proven to be the better alternative for having low power dissipation in any SRAM. In the low dimension devices, the process variations have to be considered in low power applications. In this paper data retention voltage, a parameter used for estimation of cell stability is considered and also the leakage power with a variation of transistor functionality. Cadence Virtuoso tool is used to evaluate process corner analysis with 18 nm FinFET technology. The data retention voltage in fast-slow (FS) corner is low and it is high in fast–fast (FF) corner at low temperatures and when the temperature is high FF corner has a high data retention voltage. Similarly, the leakage power is low at the TT process corner maintaining stability.

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Data availability

The datasets generated during and/or analysed during the current study are available from the first/corresponding author on reasonable request.

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  1. School of Electronics and Electrical Engineering, Lovely Professional University, Punjab, India

    T. Santosh Kumar & Suman Lata Tripathi

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  1. T. Santosh Kumar
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  2. Suman Lata Tripathi
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Correspondence to Suman Lata Tripathi.

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Kumar, T.S., Tripathi, S.L. Process evaluation in FinFET based 7T SRAM cell. Analog Integr Circ Sig Process 109, 545–551 (2021). https://doi.org/10.1007/s10470-021-01938-4

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  • DOI: https://doi.org/10.1007/s10470-021-01938-4

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