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Speed, power and area efficient 2D FIR digital filter using vedic multiplier with predictor and reusable logic

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Abstract

The main goal of this paper is to design an efficient 2D FIR digital filter for digital image processing and digital signal processing applications. To optimize filter speed, area and power different multipliers like array, Wallace tree, Booth and Vedic are used in the design of filters. Among these multipliers, Vedic multiplier reduces the partial products in multiplication. This increases the speed of the multiplication process. Vedic multiplier is based on ancient mathematics and uses a sutra called “Urdhva Tiryabhyam”. This paper, proposes two methods to optimize speed, area and power. The first method uses a predictor block in Vedic multiplier. This helps in predicting the outputs with the help of previous outputs. In the second method Reusable Logic blocks are used in Vedic multiplier. This method occupies only less number of LUTs and slice registers. The 2D FIR digital filter is designed and implemented using the two proposed multipliers and the state of art multipliers. The experimental results show that the 2D FIR digital filter using Vedic multiplier with predictor has 71.07% less EDP and using Vedic multiplier with Reusable Logic has 89.5% less EDP compared to conventional Vedic multiplier. The 2D FIR filter designed using Verilog HDL, synthesized, simulated and implemented using Xilinx FPGA. Comparison of simulation results show that 2D FIR filter implemented using the proposed methods optimizes the speed, area and power of the filter.

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Authors and Affiliations

  1. Department of Electronics and Communication, Vins Christian Women’s College of Engineering, Nagercoil, Tamil Nadu, 629003, India

    V. Dyana Christilda

  2. Department of Electronics and Communication, St. Xavier’s Catholic College of Engineering, Nagercoil, Tamil Nadu, 629003, India

    A. Milton

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  1. V. Dyana Christilda
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  2. A. Milton
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Correspondence to V. Dyana Christilda.

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Christilda, V.D., Milton, A. Speed, power and area efficient 2D FIR digital filter using vedic multiplier with predictor and reusable logic. Analog Integr Circ Sig Process 108, 323–333 (2021). https://doi.org/10.1007/s10470-021-01853-8

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  • DOI: https://doi.org/10.1007/s10470-021-01853-8

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