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A 36.7 mW, 28 GHz receiver frontend using 40 nm RFCMOS technology with improved Figure of Merit

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Abstract

High carrier frequency requirement (Sub 6, 28 GHz) to accomplish the high bandwidth specification for millimeter wave band wireless communication, has reduced the ratio of operating carrier frequency (fc) and unity current gain frequency (ft) of MOSFETs in state of the art RFCMOS technology. This poses a challenge for designing a high gain and low noise receiver with better linearity. In an attempt to realize such receiver, this paper presents a 28 GHz receiver front-end in 40 nm RFCMOS technology. It includes 3-stage low noise amplifier incorporating push pull topology, current bleeding down converting gilbert cell based mixer with common gate transconductance stage followed by a standard Gm-C filter. By incorporating these techniques, the performance of the proposed receiver improved in terms of linearity as compared to the state of the art designs. For a comprehensive analysis, the combined effect of performance parameters has been compiled into a single metric i.e. Figure of Merit (FOM). The proposed receiver exhibits conversion gain of 30.5 dB and 2.15 dB noise figure with linearity parameter IIP3 being −21.7 dBm while consuming 36.7mW power resulting in FOM value of 0.27.

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Authors and Affiliations

  1. Indian Institute of Information Technology - Allahabad, Prayagraj, Uttar Pradesh, India

    Ankita Verma, Pritesh Kumar Yadav, Sunanda Ambulker, Manish Goswami & Prasanna Kumar Misra

Authors
  1. Ankita Verma
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  2. Pritesh Kumar Yadav
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  3. Sunanda Ambulker
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  4. Manish Goswami
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  5. Prasanna Kumar Misra
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Correspondence to Ankita Verma.

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Verma, A., Yadav, P.K., Ambulker, S. et al. A 36.7 mW, 28 GHz receiver frontend using 40 nm RFCMOS technology with improved Figure of Merit. Analog Integr Circ Sig Process 107, 135–144 (2021). https://doi.org/10.1007/s10470-020-01792-w

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  • DOI: https://doi.org/10.1007/s10470-020-01792-w

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