Skip to main content
SpringerLink
Log in

A high precision logarithmic-curvature compensated all CMOS voltage reference

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

This paper presents a resistor-less high-precision, sub-1 V all-CMOS voltage reference. A curvature-compensation method is used to cancel the logarithmic temperature dependence regardless of mobility temperature exponent \((\upgamma)\). The circuit is simulated in 65 nm CMOS technology and yields an output voltage of 594 mV, temperature coefficient of \(7\frac{\text{ppm}}{{^{ \circ } {\text{C}}}}\) in the range of −40 to 125 °C, a power supply rejection ratio (PSRR) of − 43 dB at of 100 Hz, a line sensitivity of \(\frac{{76\,\upmu{\text{V}}}}{\text{V}}\) in the supply voltage range of 1.2 to 2 V, a power dissipation of \(1.4\,\upmu{\text{W}}\) at 1.2 V supply and an output noise of \(2.8\frac{{\upmu{\text{V}}}}{{\sqrt {\text{Hz}} }}\) at \(100\,{\text{Hz}}\). The total active area of the design is \(0.03\,{\text{mm}}^{2}\). This voltage reference is suitable for low-power, low-voltage applications which also require high precision.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11

Similar content being viewed by others

References

  1. Rincon-Mora, G. A. (2002). Voltage reference-from diodes to precision high-order bandgap circuits. New York: Wiley.

    Google Scholar 

  2. Banba, H., Shiga, H., Umezawa, A., Miyaba, T., Tanzawa, T., Atsumi, S., et al. (1999). A CMOS bandgapreferencecircuitwithsub-1-Voperation. IEEE Journal of Solid-State Circuits 3, 4(5), 670–674.

    Article  Google Scholar 

  3. Widlar, R. J. (1971). New developments in IC voltage regulators. IEEE Journal of Solid-State Circuits, SSC-6(1), 2–7.

    Article  Google Scholar 

  4. Rich, A. (2005). Voltage reference application and design note. Retrieved June 23, 2005 from http://www.Allelectronics.de/ai/resources/1cfd65da928.pdf.

  5. Neuteboom, H., Kup, B. M. J., & Janssens, M. (1997). A DSP-based hearing instrument IC. IEEE Journal of Solid-State Circuits, 32(11), 1790–1806.

    Article  Google Scholar 

  6. Brokaw, A. P. (1974). A simple three-terminal IC bandgap reference. IEEE Journal of Solid-State Circuits, SSC-9(6), 388–393.

    Article  Google Scholar 

  7. Leung, K. N., & Mok, P. K. T. (2002). A sub-1-V 15 ppm/C CMOS bandgap voltage reference without requiring low threshold voltage device. IEEE Journal of Solid-State Circuits, 37(4), 526–530.

    Article  Google Scholar 

  8. Doyle, J., Lee, Y. J., Kim, Y.-B., Wilsch, H., & Lombardi, F. (2004). A CMOS subbandgap reference circuit with 1-V power supply voltage. IEEE Journal of Solid-State Circuits, 39(1), 252–255.

    Article  Google Scholar 

  9. Leung, K. N., Mok, P. K. T., & Leung, C. Y. (2003). A 2-V 23u A 5.3-ppm/C curvature-compensated CMOS bandgap voltage reference. IEEE Journal of Solid-State Circuits, 38, 561–564.

    Article  Google Scholar 

  10. Rincon-Mora, G. A., & Allen, P. E. (1998). A 1.1-V current-mode and piecewise-linear curvature-corrected bandgap reference. IEEE Journal of Solid-State Circuits, 33(10), 1551–1554.

    Article  Google Scholar 

  11. Li, J.-H., Zhang, X., & Yu, M. (2011). A 1.2-V piecewise curvature-corrected bandgap reference in 0.5 mCMOS process. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(6), 1118–1122.

    Article  Google Scholar 

  12. Popa, C. (2009). Logarithmic compensated voltage reference. In Proceedings of the 2009 Spanish conference on electron devices (pp. 215–218). Santiago de Compostela, Spain, February 11–13, 2009.

  13. Duan, Q., & Roh, J. (2014). A 1.2-V 4.2-ppm C high-order curvature-compensated CMOS bandgap reference. IEEE Transactions on Circuits and Systems—I, 62(3), 662–670.

    Article  MathSciNet  Google Scholar 

  14. Lee, K., Sverre Lande, T., & Hafliger, P. (2015). A sub-bandgap reference circuit with an inherent curvature-compensation property. IEEE Transactions on Circuits and Systems—I, 62(1), 1–9.

    Article  Google Scholar 

  15. Siqueira Dias, J. A., do Amaral, W. A., & de Moraes, W. B. (2009). A curvature-compensated CMOS voltage reference using V2th characteristics. Microelectronics Journal, 40, 1772–1778.

    Article  Google Scholar 

  16. Rossi, C., Galup-Montoro, C., & Schneider, M. C. (2007). PTAT voltage generator based on an MOS voltage divider. In Proceedings of the IEEE NSIT (pp. 625–628).

  17. Tam, W Sh, Wong, O. Y., Kok, C. W., & Wong, H. (2010). Generating sub/1 V reference voltages from a resistorless CMOS bandgap reference ciecuit by using a piecewise curvature temperature compensation technique. Microelectronics Reliability Journal, 50, 1054–1061.

    Article  Google Scholar 

  18. Zeng, Y., Huang, Y., Luo, Y., & Tan, H. Z. (2013). An ultra-low-power CMOS voltage reference generator based on body bias technique. Microelectronics Journal, 44, 1145–1153.

    Article  Google Scholar 

  19. Chouhan, Sh S, & Halonen, K. (2015). Design and implementation of a micro-power CMOS voltage reference circuit based on thermal compensation of V gs. Microelectronics Journal, 46, 36–42.

    Article  Google Scholar 

  20. Luo, H., Han, Y., Cheung, R. C. C., Liang, G., & Zhu, D. (2012). Subthreshold CMOS voltage reference circuit with body bias compensation for process variation. IET Circuits, Devices & Systems, 6(3), 198–203.

    Article  Google Scholar 

  21. Osaki, Y., Hirose, T., Kuroki, N., & Numa, M. (2013). 1.2-V Supply, 100nW, 1.09-V Bandgap and 0.7-V Supply, 52.2-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs. IEEE Journal of Solid-State Circuits, 48(6), 1530–1538.

    Article  Google Scholar 

  22. Ker, M. D., & Chen, J. S. (2006). New curvature compensated technique for CMOS bandgap reference with sub-1-V operation. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 53(8), 667–671.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electrical Engineering, Shahid Chamran University of Ahvaz, Ahvaz, Iran

    Tayebeh Ghanavati Nejad, Ebrahim Farshidi & Abdolnabi Kosarian

  2. Department of Electrical and Information Technology, Lund University, Lund, Sweden

    Henrik Sjöland

Authors
  1. Tayebeh Ghanavati Nejad
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Ebrahim Farshidi
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Henrik Sjöland
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Abdolnabi Kosarian
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Tayebeh Ghanavati Nejad.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Ghanavati Nejad, T., Farshidi, E., Sjöland, H. et al. A high precision logarithmic-curvature compensated all CMOS voltage reference. Analog Integr Circ Sig Process 99, 383–392 (2019). https://doi.org/10.1007/s10470-018-1296-0

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-018-1296-0

Keywords

Search

Navigation