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Body-driven log/antilog PVT compensated analog computational block

  • Mixed Signal Letter
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An Erratum to this article was published on 03 February 2017

Abstract

A four quadrant analog multiplier is proposed in this paper. It is using body-driven MOSFETs operating in subthreshold region. In essence, the subthreshold approach is too susceptible to PVT variations. However, these effects have been intrinsically mitigated by the log/antilog characteristics and enable the realization of current-mode multiplication function in simple and power efficient way at the same time. The multiplier is designed in CMOS 0.18 µm 1P6 M process technology. It occupies an active area of 250 µm2 and consumes 0.698 µW from ± 0.3 V voltage supply. The results are in agreement with the theory under different conditions.

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References

  1. Liu, W., & Liu, S. (2010). Design of a CMOS low-power and low-voltage four-quadrant analog multiplier. Analog Integrated Circuits and Signal Processing, 63(2), 307–312.

    Article  MathSciNet  Google Scholar 

  2. Panigrahi, A., & Paul, P. K. (2013). A novel bulk-input low voltage and low power four quadrant analog multiplier in weak inversion. Analog Integrated Circuits and Signal Processing, 75(2), 237–243.

    Article  Google Scholar 

  3. Al-Tamimi, K., Thiyagarajan, P., & El-Sankary, K. (2016). Continuous-time four-quadrant modulator with inherent PVT cancellation. Electronics Letters, 52(10), 807–808.

    Article  Google Scholar 

  4. Chang, C. C., & Liu, S. I. (1998). Weak inversion four-quadrant multiplier and two-quadrant divider. Electronics Letters, 34(22), 2079–2080.

    Article  Google Scholar 

  5. Demosthenous, A., & Panovic, M. (2005). Low-voltage MOS linear transconductor/squarer and four-quadrant multiplier for analog VLSI. IEEE Transactions on Circuits and Systems I: Regular Papers, 52(9), 1721–1731.

    Article  Google Scholar 

  6. Tanno, K., Ishizuka, O., & Tang, Z. (2000). Four-quadrant CMOS current-mode multiplier independent of device parameters. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 47(5), 473–477.

    Article  Google Scholar 

  7. Yuce, E. (2008). Design of a simple current-mode multiplier topology using a single CCCII+. IEEE Transactions on Instrumentation and Measurement, 57(3), 631–637.

    Article  Google Scholar 

  8. Fried, R., & Enz, C. C. (1997). Simple and accurate voltage adder/subtractor. Electronics Letters, 33(11), 944–945.

    Article  Google Scholar 

  9. Sawigun, C., & Demosthenous, A. (2006). Compact low-voltage CMOS four-quadrant analogue multiplier. Electronics Letters, 42(20), 1149–1151.

    Article  Google Scholar 

  10. Sawigun, C., & Serdijn, W. A. (2009). Ultra-low-power, class-AB, CMOS four-quadrant current multiplier. Electronics Letters, 45(10), 483–484.

    Article  Google Scholar 

  11. Ghanavati, B., & Nowbakht, A. (2010). ±1 V high frequency four quadrant current multiplier. Electronics Letters, 46(14), 974–976.

    Article  Google Scholar 

  12. Tao, X., Liu, C., & Zhao, T. (2012). A four-quadrant analog multiplier under a single power supply voltage. Analog Integrated Circuits and Signal Processing, 71(36), 525–530.

    Article  Google Scholar 

  13. Al-Absi, M. A., Hussein, A., & TaherAbuelma’atti, M. (2013). A low voltage and low power current-mode analog computational circuit. Circuits, Systems, and Signal Processing, 32(1), 321–331.

    Article  MathSciNet  Google Scholar 

  14. Al-Suhaibani, E., & Al-Absi, M. A. (2015). A compact CMOS current-mode analog multi-functions circuit. Analog Integrated Circuits and Signal Processing, 84, 471–477.

    Article  Google Scholar 

Download references

Acknowledgements

Acknowledgment is due Hadhramout Establishment for Human Development (HEHD), Hadhramout, Yemen. The authors would also like to thank Pavithera Thiyagarajan for her valuable help in simulation and layout.

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Authors and Affiliations

  1. Microelectronics & VLSI Research Laboratory, Electrical and Computer Engineering Department, Dalhousie University, Barrington St, Halifax, NS, 1360, Canada

    Karama M. AL-Tamimi & Kamal EL-Sanakary

Authors
  1. Karama M. AL-Tamimi
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  2. Kamal EL-Sanakary
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Correspondence to Karama M. AL-Tamimi.

Additional information

An erratum to this article is available at http://dx.doi.org/10.1007/s10470-017-0929-z.

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AL-Tamimi, K.M., EL-Sanakary, K. Body-driven log/antilog PVT compensated analog computational block. Analog Integr Circ Sig Process 90, 693–700 (2017). https://doi.org/10.1007/s10470-016-0909-8

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  • DOI: https://doi.org/10.1007/s10470-016-0909-8

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