Abstract
We propose a novel floorplanning algorithm for 3D ICs with through-silicon vias (TSVs) that directly optimizes delay due to wires and TSVs. We include the non-negligible impact of area occupied by TSVs, perform nets-to-TSVs assignment, and use physical dimensions of TSVs and wires for delay calculations. Our floorplanning is based on co-placement of TSV islands with circuit blocks and is performed under fixed-outline constraints. The total delay is a direct optimization goal in the presented delay-aware 3D floorplanning and accounts for the RC delay impact of TSVs on the delay of each individual net during the nets-to-TSVs assignment. Therefore, compared to traditional wirelength-aware floorplanning, which separately minimize wirelength and the number of TSVs, the proposed approach results in more effective delay minimization. Our experimental results show improved solution quality with up to 9 % shorter wirelength and an average 40 % reduction in the number of TSVs as compared to most recent publications. Total delay reduces between 10 and 12 % when the delay, instead of wirelength and the number of TSVs separately, is minimized.
Similar content being viewed by others
References
Ahmed, M. A., & Chrzanowska-Jeske, M. (2012). TSVs in early layout design exploration for 3D ICs. In IEEE 5th Latin American symposium on circuits and systems (LASCAS) (pp. 25–28).
Ahmed, M. A., & Chrzanowska-Jeske, M. (2014). Delay and power optimization with TSV-aware 3D floorplanning. In Proceedings of the IEEE 15th international symposium on quality electronic design (ISQED) (pp. 189–19).
Ahmed, M. A., Mohapatra, S., & Chrzanowska-Jeske, M. (2014). 3D floorplanning with nets-to-TSVs assignment. In 21st IEEE international conference on electronics circuits and systems (ICECS) (pp. 578–581).
Avci, M., & Yamacli, S. (2010). An improved Elmore delay model for VLSI interconnects. An International Journal on Mathematical and Computer Modeling, 51, 908–914.
Chen, S., & Yoshimura, T. (2010). Multilayer floorplanning for stacked ICs: Configuration number and fixed-outline constraints. Integration, VLSI Journal, 43(4), 378–388.
Cong, J., Wei, J., & Zhang, Y. (2004). A thermal-driven floorplanning algorithm for 3-D ICs. In Proceedings of the IEEE international conference computer-aided design (pp. 306–313).
Elmore, W. C. (1948). The transient response of damped linear network with particular regard to wideband amplifiers. Journal of Applied Physics, 19, 55–63.
Khalil, D., Ismail, Y., Khellah, M., Karnik, T., & De, V. (2008). Analytical model for propagation delay of through silicon vias. In Proceedings of the international symposium on quality electronic design (pp. 553–556).
Kim, D. H., & Lim S. K. (2010). Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs. In SLIP’10 proceedings of the 12th ACM/IEEE international workshop on system level interconnect prediction (pp 25–32).
Kim, D. H., Athikulwongse, K., & Lim, S. K. (2013). Study of through-silicon-via impact on the 3-D stacked IC layout. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(5), 862–874.
Kim, D. H., Mukhopadhyay, S., & Lim, S. K. (2011). Fast and accurate analytical modeling of through-silicon-via capacitive coupling. IEEE Transactions on Component Packaging, Manufacturing Technology, 1(2), 168–180.
Kim, B., Sharbono, C., Ritzdorf, T., & Schmauch D. (2007). Factors affecting copper filling process whithin high aspect ratio deep vias for 3D chip stacking. In: Proceedings of the 57th electronic components and technology conference (pp. 838–843). Reno.
Knechtel, J., Markov, I. L., & Lienig, J. (2012). Assembling 2-D blocks into 3-D chips. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(2), 228–241.
Lee, Y. J., Lim, S. K. (2012). Fast delay estimation with buffer insertion for through-silicon-via-based 3D interconnects. In 2012 13th international symposium on quality electronic design (ISQED) (pp. 228–335). March 19–21, 2012.
Li, Z., Hong, X., Zhou, Q., Cai, Y., Bian, J., Yang, H. H., et al. (2006). Hierarchical 3-D floorplanning algorithm for wirelength optimization. IEEE Transactions on Circuits Systems I: Regular Papers, 53(12), 2637–2646.
Li, C. R., Mak, W. K., & Wang, T. C. (2013). Fast fixed-outline 3-D IC floorplanning with TSV co-placement. IEEE Transactions on VLSI Systems, 21(3), 523–532.
Nain, R. K., & Chrzanowska-Jeske, M. (2011). Fast placement aware 3-D floorplanning using vertical constraints on sequence pairs. IEEE Transactions on VLSI Systems, 19, 1667–1680.
Sakurai, T., & Tamaru, K. (1983). Simple formulas for two- and three-dimensional capacitances. IEEE Transactions on Electron Devices, 30(2), 183–185.
Savidis, I., & Friedman, E. G. (2009). Closed-form expressions of 3D via resistance, inductance, and capacitance. IEEE Transactions on Electron Devices, 56(9), 1873–1881.
Semiconductor Industry Association (2012) International technology roadmap for semiconductors.
Tsai, M. C., Wang, T. C., & Hwang, T. T. (2011). Through-silicon via planning in 3-D floorplanning. IEEE Transactions on VLSI Systems, 19(8), 1448–1457.
Zhou, P., Ma, Y., Li, Z., Dick, R. P., Shang, L., Zhou, H., Zhou, Q., & Hong, X. (2007). 3-D-STAF: Scalable temperature and leakage aware floorplanning for 3-D integrated circuits. In Proceedings of the IEEE international conference computer-aided design (pp. 590–597).
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Ahmed, M.A., Mohapatra, S. & Chrzanowska-Jeske, M. TSV- and delay-aware 3D-IC floorplanning. Analog Integr Circ Sig Process 87, 235–248 (2016). https://doi.org/10.1007/s10470-016-0717-1
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10470-016-0717-1