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Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS

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Abstract

This paper presents a 15-bit, two-stage pipelined successive approximation register analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier while eliminating excessive capacitive load and consequent power consumption. An elaborate power consumption analysis of the entire ADC was performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitor-based DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-μm CMOS process, the prototype ADC achieves a peak SNDR of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8 bits at a sampling frequency of 1 kS/s and provides an FoM of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB >12.1 bits upto the Nyquist bandwidth of 500 Hz while consuming 6.7 μW. Core area of the ADC is 0.679 mm2.

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Authors and Affiliations

  1. Department of Electrical Engineering, Linköping University, Linköping, Sweden

    Kairang Chen, Prakash Harikumar & Atila Alvandpour

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  1. Kairang Chen
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  2. Prakash Harikumar
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  3. Atila Alvandpour
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Correspondence to Kairang Chen.

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Chen, K., Harikumar, P. & Alvandpour, A. Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-μm CMOS. Analog Integr Circ Sig Process 86, 87–98 (2016). https://doi.org/10.1007/s10470-015-0648-2

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  • DOI: https://doi.org/10.1007/s10470-015-0648-2

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