Abstract
A new open loop, high resolution CMOS sample and hold (S/H) circuit is introduced in this article. This circuit is constructed based on a new method which leads to a great reduction in dependency of the storing charge of the holding capacitors to the charge injection of transistors. It is a combination of dummy switches and auxiliary capacitors in order to decrease the voltage spikes that are produced during the sampling mode. Due to the high linearity feature of our proposed design in comparison with previous works, it is reached to a great improvement in signal to noise and distortion ratio up to about 15 dB and it’s ENOB is equivalent with about 16 bits. Another advantages of our proposed design are it’s lower power dissipation and it’s high input voltage range. Also the optimum functionality of our proposed circuit does not damaged by the threshold voltage’s variations in different corners. As our proposed S/H circuit has been designed in open loop structure, it is suitable for high speed applications.
Similar content being viewed by others
References
Hadidi, K. H., Sasaki, M., Watanabe, T., Muramatsu, D., & Matsumoto, T. (1998). An open-loop full CMOS 103 MHz −61 dB THD S/H circuit. The IEEE Custom Integrated Circuits Conference (pp. 381–3). Santa Clara, USA.
Hadidi, K. H., Muramatsu, D., Oue, T., & Matsumoto, T. (1999). A 500 MS/s −54 dB THD S/H circuit in a 0.5 um CMOS process. 25th European solid-state circuits conference (pp. 158–61). Duisburg, Germany.
Mousazadeh, M., Hadidi, K. H., & Khoei, A. (2008). A novel open-loop high-speed CMOS sample-and-hold. AEU International Journal of Electronics and Communi-cations, 62(8), 588–596.
Schillaci, L., Baschirotto, A., & Castello, R. (1997). A 3-V 5.4 mW BiCMOS track and hold circuit with sampling frequency up to 150 MHz. IEEE Journal of Solid-State Circuits, 32, 926–932.
Razavi, B., & Sung J. (1995). A 200 MHz BICMOS sample-and-hold amplifier with 3 V supply. IEEE Internati-onal Solid-state Circuits Conference, Digest of Technical Papers (pp. 56–57). San Francisco, CA.
Hadidi, K. H., & Khoei, A. (1996). A highly linear cascade driver CMOS source follower buffer. Proceedings of Third International Conference on Electronics, Circuits and Systems (pp. 128–132). Rodos, Greece.
Razavi, B. (2001). Design of analog CMOS integrated circuit. McGraw-Hill Series in Electrical and Computer Engineering.
Razavi, B. (1995). Principles of data conversion system design. New York: IEEE Press.
Hadidi, K. H., Sobhi, J., Hasankhan, A., Muramatsu, D., & Matsumoto, T. (1998). A novel highly linear cmos buffer. The 5th IEEE International Conference on Electronics, Circuit and Systems (pp. 369–71). Lisbon, Portugal.
Sawigun, C., & Serdijn, W. A. (2011). Analysis and design of a low-voltage, low-power, high-precision, class-AB current-mode subthreshold CMOS sample and hold circuit. IEEE Transactions on Circuits and Systems I, 58, 1615–1626.
Trivedi, R. (2006). Low power and high speed sample-and-hold circuit. IEEE International Midwest Symposium on Circuits and Systems. MWSCAS ‘06. 49th, vol.1, pp.453–456.
Mah, S. L. Chan, P. K. & Mishra, S. K.(2010). A precision low-power mismatch-compensated sample-and-hold circuit for biomedical applications. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) (pp. 192–195).
Reddy, Y. S. G., & Liter, S. (2012). A 1.2 V 80MS/S sample and hold for ADC applications. International Conference on Devices, Circuits and Systems (ICDCS) (pp.15–19).
Boni, A., Pierazzi, A., & Morandi, C. (2001). A 10-b 185 MS/s track-and-hold in 0.35 μm CMOS. IEEE Journal of Solid-State Circuits, 36(2), 195–203.
Lee, T.-S., & Lu, C.-C. (2005). A 1.5-V 50-MHz pseudodifferential CMOS sample-and-hold circuit with low hold pedestal. IEEE Transactions on Circuits and Systems I, 52, 1752–1757.
Balachandran, G. K., & Allen, P. E. (2001). Fully differential switched-current memory cell with low charge-injection errors. IEE Proceedings Circuits Devices and Systems, 148(3), 157–163.
Sugimoto, Y., & Haigh, D. G. (2008). A current-mode circuit with a linearized input V/I conversion scheme and the realization of a 2/2.5 V operational, 100MS/s, MOS SHA. IEEE Transactions on Circuits and Systems I, 55(8), 2178–2187.
Harpe, P., & Zanikopoulos, A., Hegt, H. van Roermund, A. (2006). A 62 dB SFDR, 500 MSPS, 15 mW open-loop track-and-hold circuit. 24th Norchip Conference (pp. 103–106).
Sadollahy, M., & Hadidi, K. (2008). High-speed highly-linear CMOS S/H circuit. International Conference on Computer and Communication Engineering (ICCCE) (pp. 550–553).
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Abolhasani, A., Tohidi, M., Hadidi, K. et al. A new high-speed, high-resolution open-loop CMOS sample and hold. Analog Integr Circ Sig Process 78, 409–419 (2014). https://doi.org/10.1007/s10470-013-0158-z
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10470-013-0158-z