Skip to main content
SpringerLink
Log in

Putting it all together – Formal verification of the VAMP

  • Special section on Recent Advances in Hardware Verification
  • Published:
International Journal on Software Tools for Technology Transfer Aims and scope Submit manuscript

Abstract

In the verified architecture microprocessor (VAMP) project we have designed, functionally verified, and synthesized a processor with full DLX instruction set, delayed branch, Tomasulo scheduler, maskable nested precise interrupts, pipelined fully IEEE compatible dual precision floating point unit with variable latency, and separate instruction and data caches. The verification has been carried out in the theorem proving system PVS. The processor has been implemented on a Xilinx FPGA.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. The VAMP project. Website: http://www-wjp.cs.uni-sb.de/projects/verification

  2. Berg, C.: Formal verification of an IEEE floating point adder. Master’s Thesis, Saarland University, Germany (2001)

  3. Berg, C., Jacobi, C.: Formal verification of the VAMP floating point unit. In: Proceedings of the 11th CHARME, vol. 2144 of LNCS, pp. 325–339. Springer, Heidelberg (2001)

  4. Berg, C., Jacobi, C., Kröning, D.: Formal verification of a basic circuits library. In: IASTED International Conference on Applied Informatics. ACTA Press (2001)

  5. Bevier, W.R., Hunt, W.A., Moore, J.S., Young, W.D.: An approach to systems verification. J. Autom. Reason. 5, 411–428 (1989)

    Google Scholar 

  6. Beyer, S.: Putting it all together – Formal verification of the VAMP. PhD Thesis, Saarland University, Germany (2005)

  7. Beyer, S., Jacobi, C., Kröning, D., Leinenbach, D.: Correct hardware by synthesis from PVS. Internal Report, available at http://www-wjp.cs.uni-sb.de/publikationen/BJKL02.pdf (2002)

  8. Beyer, S., Jacobi, C., Kröning, D., Leinenbach, D., Paul, W.: Instantiating uninterpreted functional units and memory system: Functional verification of the VAMP. In: Geist, D., Tronci, E. (eds.) CHARME 2003, vol. 2860 of LNCS, pp. 51–65. Springer, Heidelberg (2003)

  9. Brock, B., Hunt, W.A., Kaufmann, M.: The FM9001 microprocessor proof. Technical Report Technical Report 86, Computational Logic Inc. (1994)

  10. Brock, B.C., Hunt, W.A.: The DUAL-EVAL hardware description language and its use in the formal specification and verification of the FM9001 microprocessor. Form. Methods Syst. Des. 11, 71–107 (1997)

    Article  Google Scholar 

  11. Burch, J.R., Dill, D.L.: Automatic verification of pipelined microprocessors control. In: CAV 94, vol. 818, pp. 68–80. Springer-Verlag, Standford, CA (1994)

  12. Butler, R.W., Miner, P.S., Srivas, M.K., Greve, D.A., Miller, S.P.: A bitvectors library for PVS. Technical Report 110274, NASA Langley Research Center (1996)

  13. Chen, Y.-A., Clarke, E.M., Ho, P.-H., Hoskote, Y., Kam, T., Khaira, M., O’Leary, J.W., Zhao, X.: Verification of all circuits in a floating-point unit using word-level model checking. In: FMCAD, vol. 1166 of LNCS, pp. 19–33. Springer, Heidelberg (1996)

  14. Damm, W., Pnueli, A.: Verifying out-of-order executions. In: Charme IFIP WG10.5, pp. 23–47. Chapman & Hall, Montreal, Canada (1997)

  15. Eiriksson, A.P.: The formal design of 1M-gate ASICs. In: Gopalakrishnan, G., Windley, P. (eds.) FMCAD 98, vol. 1522 of LNCS, pp. 49–63. Springer, Heidelberg (1998)

  16. Emerson, E.A., Clarke, E.M.: Characterizing correctness properties of parallel programs using fixpoints. In: Automata, Languages and Programming, vol. 85 of LNCS. Springer, Heidelberg (1980)

  17. Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach, 2nd edn. Morgan Kaufmann, San Mateo, CA (1996)

    MATH  Google Scholar 

  18. Hillebrand, M.: Address spaces and virtual memory: Specification, implementation, and correctnesss. PhD Thesis, Saarland University, Germany (2005)

  19. Hosabettu, R., Srivas, M., Gopalakrishnan, G.: Proof of correctness of a processor with reorder buffer using the completion functions approach. In: Computer-Aided Verification, CAV ’99, vol. 1633, pp. 47–59. Springer-Verlag, Trento, Italy (1999)

  20. Hunt, W.A., Sawada, J.: Verifying the FM9801 microarchitecture. IEEE Micro, pp. 47–55 (1999)

  21. Institute of Electrical and Electronics Engineers. ANSI/IEEE standard 754–1985, IEEE Standard for Binary Floating-Point Arithmetic (1985)

  22. Jacobi, C.: A formally verified theory of IEEE rounding. Unpublished, available at http://www-wjp.cs.uni-sb.de/~cj/ieee-lib.ps (2001)

  23. Jacobi, C.: Formal verification of complex out-of-order pipelines by combining model-checking and theorem-proving. In: CAV, vol. 2404 of LNCS. Springer, Heidelberg (2002)

  24. Jacobi, C.: Formal verificaton of a fully IEEE compliant floating point unit. PhD Thesis, Saarland University, Germany (2002)

  25. Jacobi, C., Berg, C.: Formal verification of the VAMP floating point unit. In: Formal Methods in System Design, pp. 227–266. Springer (May 2005)

  26. Jacobi, C., Weber, K., Paruthi, V., Baumgartner, J.: Automatic formal verification of fused-multiply-add FPUs. In DATE, pp. 1298–1303. IEEE Computer Society (2005)

  27. Karatsuba, A., Ofman, Y.: Multiplication of multidigit numbers on automata. Sov. Phys. Dokl. 7 (1963)

  28. Kröning, D.: Formal verification of pipelined microprocessors. PhD Thesis, Saarland University, Germany (2001)

  29. Kröning, D., Müller, S., Paul, W.: Proving the correctness of pipelined micro-architectures. In: 3ITG-/GI/GMM-Workshop Methoden und Beschreibungsprachen zur Modellierung und Verifikation von Schaltungen und System, pp. 89–98. VDE Verlag (2000)

  30. Kröning, D., Müller, S., Paul, W.: Proving the correctness of processors with delayed branch using delayed PCs. Numbers, Information and Complexity, pp. 579–588 (2000)

  31. Kröning, D., Paul, W.: Automated pipeline design. In: Proceedings of the 38th Design Automation Conference, pp. 810–815. ACM Press, New York (2001)

  32. Leinenbach, D.: Implementierung eines maschinell verifizierten Prozessors. Master’s Thesis, Saarland University, Germany (2002)

  33. McMillan, K.: Verification of an implementation of Tomasulo’s algorithm by compositional model checking. In: CAV 98, vol. 1427. Springer, Heidelberg (1998)

  34. McMillan, K.: Parameterized verification of the FLASH cache coherence protocol by compositional model checking. In: CHARME 2001, vol. 2144 of LNCS. Springer, Heidelberg (2001)

  35. Meyer, C.: Entwicklung einer Laufzeitumgebung für den VAMP-Prozessor. Master’s Thesis, Saarland University, Germany (2002)

  36. Miner, P.S.: Defining the IEEE-854 floating-point standard in PVS. Technical Report TM-110167, NASA Langley Research Center (1995)

  37. Müller, S.M., Paul, W.J.: Computer architecture. Complexity and correctness. Springer, Heidelberg (2000)

    MATH  Google Scholar 

  38. O’Leary, J., Zhao, X., Gerth, R., Seger, C.-J.H.: Formally verifying IEEE compliance of floating-point hardware. Intel Technol. J., Q1 (1999)

  39. Owre, S., Shankar, N., Rushby, J.M.: PVS: A prototype verification system. In: CADE 11, vol. 607 of LNAI, pp. 748–752. Springer, Heidelberg (1992)

  40. Russinoff, D.M.: A mechanically checked proof of IEEE compliance of the floating point multiplication, division and square root algorithms of the AMD-K7 processor. LMS J. Comput. Math. 1, 148–200 (1998)

    MathSciNet  Google Scholar 

  41. Russinoff, D.M.: A case study in formal verification of register-transfer logic with ACL2: The floating point adder of the AMD Athlon processor. In: FMCAD-00, vol. 1954 of LNCS. Springer, Heidelberg (2000)

  42. Sawada, J., Hunt, W.A.: Trace table based approach for pipelined microprocessor verification. In: CAV 97, vol. 1254 of LNCS. Springer, Heidelberg (1997)

  43. Sawada, J., Hunt, W.A.: Processor verification with precise exceptions and speculative execution. In: CAV 98, vol. 1427 of LNCS. Springer, Heidelberg (1998)

  44. Sawada, J., Hunt, W.A.: Verification of the FM9801 microprocessor: An out-of-order microprocessor model with speculative execution, exceptions, and self-modifying code. Form. Methods Syst. Des. 20(2), 187–222 (2002)

    Article  Google Scholar 

  45. Shen, X., Arvind, Rudolph, L.: CACHET: An adaptive cache coherence protocol for distributed shared-memory systems. In: International Conference on Supercomputing (1999)

  46. Slobodova, A., Nagalla, K.: Formal verification of floating point multiply add on Itanium processors. In: Workshop on Designing Correct Circuits (2004)

  47. Stoy, J., Shen, X., Arvind: Proofs of correctness of cache-coherence protocols. In: FME, vol. 2021 of LNCS. Springer, Heidelberg (2001)

  48. Velev, M.N., Bryant, R.E.: Superscalar processor verification using efficient reductions of the logic of equality with uninterpreted functions to propositional logic. In: CHARME, vol. 1703 of LNCS. Springer, Heidelberg (1999)

  49. Velev, M.N., Bryant, R.E.: Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction. In: DAC. ACM (2000)

Download references

Author information

Authors and Affiliations

  1. OneSpin Solutions GmbH, 80339, Munich, Germany

    Sven Beyer

  2. Computer Science Department, Saarland University, 66123, Saarbrücken, Germany

    Dirk Leinenbach & Wolfgang J. Paul

  3. IBM Deutschland Entwicklung GmbH, 71032, Böblingen, Germany

    Christian Jacobi

  4. ETH Zürich, Computer Systems Institute, Zürich, Switzerland

    Daniel Kröning

Authors
  1. Sven Beyer
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Christian Jacobi
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Daniel Kröning
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Dirk Leinenbach
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Wolfgang J. Paul
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Sven Beyer.

Additional information

A shorter version of this article with the title “Instantiating uninterpreted functional units and memory system: functional verification of the VAMP” appeared in [8]. The work reported here was done while all the authors were with Saarland University.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Beyer, S., Jacobi, C., Kröning, D. et al. Putting it all together – Formal verification of the VAMP. Int J Softw Tools Technol Transfer 8, 411–430 (2006). https://doi.org/10.1007/s10009-006-0204-6

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10009-006-0204-6

Keywords

Search

Navigation