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A survey of recent advances in SAT-based formal verification

  • Special section on Bounded Model Checking
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Abstract

Dramatic improvements in SAT solver technology over the last decade and the growing need for more efficient and scalable verification solutions have fueled research in verification methods based on SAT solvers. This paper presents a survey of the latest developments in SAT-based formal verification, including incomplete methods such as bounded model checking and complete methods for model checking. We focus on how the surveyed techniques formulate the verification problem as a SAT problem and how they exploit crucial aspects of a SAT solver, such as application-specific heuristics and conflict-driven learning. Finally, we summarize the noteworthy achievements in this area so far and note the major challenges in making this technology more pervasive in industrial design verification flows.

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  1. Fujitsu Laboratories of America, Sunnyvale, CA, USA

    Mukul R. Prasad

  2. Johannes Kepler University, Linz, Austria

    Armin Biere

  3. NEC Laboratories of America, Princeton, NJ, USA

    Aarti Gupta

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Prasad, M., Biere, A. & Gupta, A. A survey of recent advances in SAT-based formal verification. Int J Softw Tools Technol Transfer 7, 156–173 (2005). https://doi.org/10.1007/s10009-004-0183-4

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