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Sorting networks on FPGAs

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Abstract

Computer architectures are quickly changing toward heterogeneous many-core systems. Such a trend opens up interesting opportunities but also raises immense challenges since the efficient use of heterogeneous many-core systems is not a trivial problem. Software-configurable microprocessors and FPGAs add further diversity but also increase complexity. In this paper, we explore the use of sorting networks on field-programmable gate arrays (FPGAs). FPGAs are very versatile in terms of how they can be used and can also be added as additional processing units in standard CPU sockets. Our results indicate that efficient usage of FPGAs involves non-trivial aspects such as having the right computation model (a sorting network in this case); a careful implementation that balances all the design constraints in an FPGA; and the proper integration strategy to link the FPGA to the rest of the system. Once these issues are properly addressed, our experiments show that FPGAs exhibit performance figures competitive with those of modern general-purpose CPUs while offering significant advantages in terms of power consumption and parallel stream evaluation.

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Authors and Affiliations

  1. IBM Almaden Research Center, San Jose, CA, USA

    Rene Mueller

  2. Systems Group, Department of Computer Science, ETH, Zurich, Switzerland

    Jens Teubner & Gustavo Alonso

Authors
  1. Rene Mueller
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  2. Jens Teubner
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  3. Gustavo Alonso
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Corresponding author

Correspondence to Rene Mueller.

Additional information

The work reported in this article was done while Rene Mueller was at ETH Zurich.

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Mueller, R., Teubner, J. & Alonso, G. Sorting networks on FPGAs. The VLDB Journal 21, 1–23 (2012). https://doi.org/10.1007/s00778-011-0232-z

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  • DOI: https://doi.org/10.1007/s00778-011-0232-z

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