Memristive self-learning logic circuit with application to encoder and decoder

Abstract

Different logic circuits based on memristors have been extensively investigated. However, most of these circuits require accurate initialization. A self-learning logic circuit based on mermristors that can achieve various logic gates without initialization is proposed in this paper. Three functional blocks, including a sum block, a learning block, and a compare block, are elaborately designed in the proposed logic circuit. Programmable switches in the sum and compare blocks enable the circuit to perform various logic gates, such as Boolean, IMPLY, and random logical combinations. In these various logical operations, the learning block can automatically obtain different memristance states. The aforementioned logic operations can easily be extended to multi-fan-in logic and logical cascade operations. Circuit designs of an encoder and decoder are considered as application examples. Finally, PSpice simulation results of the logic circuits and extended applications are provided. Simulation results indicate that the proposed circuit can effectively perform different logic operations and exhibits excellent robustness to circuit device variations.

1 Introduction

As compared with conventional CMOS technology, memristors perform several advantages such as high density, nonvolatility, low power, and good scalability [15, 34]. Therefore, logic circuits based on memristors have become a popular research topic among scholars [2, 5, 11, 13, 17, 25, 32, 36, 38]. In recent years, several memristor-based logical circuit design methods have been put forward, including material implication memristor logic (IMPLY) [22, 27,28,29, 33, 35], memristor-ratioed logic (MRL) [19, 23, 26, 30], stateful memristor logic [14, 18, 22] memristor-aided logic (MAGIC) [16, 31], memristor threshold logic (MTH) [7,8,9, 21, 24], CMOS-like memristor complementary logic (CMCL) [1, 3, 20], and memristor-as-driver gates (MAD) [10].

In 2010, the paper published by HP laboratories [4] first mentioned that a simple circuit consisting of memristors and resistors can realize the material implication logic operation (IMP), and then combining with the FALSE operation to make up a computationally complete logic unit and realize the operation of any Boolean logic function. However, the main drawback of the IMP logic lies in performing lengthy sequences. Later, a design method similar to the IMP logic circuit was proposed, that is, the memristor-aided logic (MAGIC)[16]. MAGIC-based logic gate includes two sequential stages. The first stage is to initialize the output memristor to the specified memristance. The second stage is to apply voltage $V_0$ at the gateway. If the voltage (or current) across the output memristor exceeds the threshold voltage (or current), the logic state of the output memristor will change, otherwise the state of the memristor will remain unchanged. Whether it is IMP logic or MAGIC, the logic gates require a series of sequences to operate the logic function. This implies that the complexity of the circuits is increased.

In 2011, a memristor ratioed logic (MRL) was proposed by Lehtonen [30] in their study. Any logic function can be achieved by using memristor and traditional CMOS buffers in MRL gate. The programmable resistance of memristive devices was used for the computation of Boolean AND/OR functions with voltage as the state variable, hence it avoids the drawbacks of reducing the integration efficiency in memory. Inspired by the synaptic action of neurotransmitter flow in biological brain, memory threshold logic (MTL) circuit was proposed [8, 9, 12]. These threshold logic circuits were designed to cross the boundary of Moore’s law at the device, circuit and system level, to enable high-performance systems in terms of power, energy, area, and delay. Memristors-as-drivers (MAD) gates was proposed by Lauren Guckert [10], which overcomes the shortcomings in terms of scalability, applicability, completeness, and performance by combining sense circuitry with the IMPLY operation. By sensing the values of the input memristors as the driver for the output memristor, the delay is reduced to a single step. Muayad Aljafar [1] proposed a programmable logic device, CMOS-memristive programmable logic, which is connected with the CMOS XOR to realize the multi-output function.

From the above analysis, we can see that the most existing memristor-based logic circuits require initialization as an essential operation before logic calculations. In addition, these circuits are non-uniform and difficult to extend. This paper contributes to the design of a universal memristor-based logic circuit with self-learning ability. Our design is a full-function logic circuit. Various types of logic can be achieved in a unified circuit design. The problem of initialization in traditional memristor logic circuit can be solved by self-learning adjustment in the proposed circuits. The proposed logic circuits can be extended to multi-fan-in logic easily. The ability to develop a large number of input gates can be applied in Encoder and Decoder.

The rest of the study is organized as follows. The memristive learning block and logic circuit are described in Sects. 2 and 3, respectively. The design of the complex advanced logic circuit is demonstrated in Sect. 4. In Sect. 5, circuit designs of an encoder and decoder are provided as application examples. Finally, this study is summarized in Sect. 6.

2 Memristor-based learning block

Traditional memristor logic circuits are designed with resistive switching to provide high and low resistance states. By contrast, the memristor-based self-learning circuit proposed in this work applies a threshold voltage character.

Fig. 1

Basic memristor learning circuit

The proposed memristor-based learning block is shown in Fig. 1; here, one port of two anti-parallel connected memristors (i.e., $M_a$ and $M_b$) is connected to a voltage source $V_\mathrm{in}$, and the other ports are linked to a resistor R in series. The $V_\mathrm{in}$–$V_\mathrm{out}$ relationship can be calculated as follows:

$$\begin{aligned} V_\mathrm{out}=V_\mathrm{in}\times \frac{R}{M_a//M_b+R}. \end{aligned}$$

(1)

The voltage across memristors $M_a$ and $M_b$ is

$$\begin{aligned} V_{M}=V_\mathrm{in}-V_\mathrm{out}=V_\mathrm{in}\times \frac{M_a//M_b}{ M_a//M_b+R}. \end{aligned}$$

(2)

Assume that $V_{p}$ and $V_{n}$ are positive and negative threshold voltages of the memristor, respectively, and $V_T=\mathrm{min} \left\{ V_p, \left| V_n\right| \right\}$. When the input pulse voltage $V_\mathrm{in}$ is adequately high, (i.e., the terminal voltage $\left| V_{M}\right| >V_T$), the resistance of one memristor increases while that of the other memristor decreases. The parallel resistance $M_{ab}$ ($M_a//M_b$) can only decrease because it is always lower than the resistance of the two memristors, thereby resulting in a decline in the terminal voltage $V_{M}$. If the voltage across the memristors $V_{M}$ achieves the state $V_T$ or $-V_T$ before $M_{a}$, $M_{b}$ gets to $R_\mathrm{off}$ and $R_\mathrm{on}$, and $V_{M}$ is unable to change the resistance of either of the two memristors. Hence, the circuit achieves a steady state that the output voltage meets

$$\begin{aligned} V_\mathrm{out}={\left\{ \begin{array}{ll} V_{\mathrm{in}+}-V_T, &{} \text { if } V_\mathrm{in}=V_{\mathrm{in}+}>0 \\ V_{\mathrm{in}-}+V_T,&{} \text { if } V_\mathrm{in}=V_{\mathrm{in}-}<0, \end{array}\right. } \end{aligned}$$

(3)

where $V_{\mathrm{in}+}$ and $V_{\mathrm{in}-}$ are the positive and negative values of the input pulse signal $V_\mathrm{in}$, respectively. Accordingly, R satisfies the following condition

$$\begin{aligned} \left( \frac{V_\mathrm{in}}{V_T}-1 \right) R_\mathrm{on} \le R < R_\mathrm{off}. \end{aligned}$$

(4)

Notably, $V_{\mathrm{in}+}$ and $V_{\mathrm{in}-}$ can stabilize the circuit because the two memristors (i.e., $M_a$ and $M_b$) are in reverse parallel. The steady state can be maintained even if the input $V_\mathrm{in}$ is converted from $V_{\mathrm{in}+}$ ($V_{\mathrm{in}-}$) to $V_{\mathrm{in}-}$ ($V_{\mathrm{in}+}$). Once the circuit achieves a steady state, the memristances of memristor $M_a$ and $M_b$ can remain constant, as the voltage $V_M$ at this point is $V_T$ or $-V_T$. If $V_{T}$ or $-V_{T}$ is set as a target, the circuit approaches a stable state $V_\mathrm{out}=V_{\mathrm{in}+}-V_T$ or $V_\mathrm{out}=V_{\mathrm{in}-}+V_T$ with the proper resistor R condition after some calibration stages. These stages are considered learning levels to discover a stable output voltage. Thus, the circuit shown in Fig. 1 is used as a memristor-based learning block.

Fig. 2

I–V characteristics for cyclic sweep voltage input. a The applied cyclic sweep voltage, b change in memristance

PSpice simulations are performed using a AgInSbTe memristor. A voltage-controlled threshold memristor model was proposed in [37] to effectively fit the experiment data of an actual AgInSbTe memristor. The mathematical expressions of this model are

$$\begin{aligned} M(t)&=R_\mathrm{on}\frac{\omega (t)}{D}+R_\mathrm{off}\left( 1-\frac{\omega (t)}{D}\right) , \end{aligned}$$

(5)

$$\begin{aligned} \frac{\mathrm{d}\omega (t)}{\mathrm{d}t}&= \left\{ \begin{aligned}&\mu _v\frac{R_\mathrm{on}}{D}\frac{i_\mathrm{off}}{i(t)-i_0}f(\omega (t)),&0<V_{p}<V(t)&\\&0,&V_{n}\le V(t) \le V_{p}&\\&\mu _v\frac{R_\mathrm{on}}{D}\frac{i(t)}{i_\mathrm{on}}f(\omega (t)),&V(t)<V_{n}<0&, \end{aligned} \right. \end{aligned}$$

(6)

$$\begin{aligned} f(\omega (t))&=1-\left( \frac{2\omega (t)}{D}-1\right) ^{2p}. \end{aligned}$$

(7)

The model parameters used to describe the AgInSbTe memristor are $V_{n}=-0.37~\mathrm V$, $V_{p}=0.35~\mathrm V$, $i_\mathrm{off}=1\times 10^{-5}~\mathrm A$, $i_\mathrm{on}=1~\mathrm A$, $i_{o}=1\times 10^{-3}~\mathrm A$, $\mu _{v}=1.6\times 10^{-16}~\mathrm m^2s^{-1}\Omega ^{-1}$, $D=3~\mathrm nm$. The simulated I–V characteristics of the proposed model for cyclic sweep voltage inputs are shown in Fig. 2. As shown in the figure, when the applied voltage does not exceed the threshold voltage, the memristance remains constant.

The times of ON ($R_\mathrm{off}\rightarrow R_\mathrm{on}$) $T_\mathrm{ON}$ and OFF ($R_\mathrm{on}\rightarrow R_\mathrm{off}$) $T_\mathrm{OFF}$ under switching different applied voltages are given in Fig. 3a, b, respectively. The ON switching state or OFF switching state of the memristor is set to $x = 0.96$ or $x = 0.03$. Figure 3 shows that the switching time gradually decreases as the applied voltage increases. Then, increasing the voltage increases the switching speed. When the applied constant voltage is 1.5 V or $-1.5$ V, $T_\mathrm{ON}$ or $T_\mathrm{OFF}$ is 0.11 ms or 0.098 ms.

Fig. 3

Switching behavior. The changes in state variable x with time when applying different constant voltages. a ON switching, b OFF switching

The simulation results of the memristor-based learning circuit with two different pulse input cases (1 and 2) when $V_{\mathrm{in}+}=\left| V_{\mathrm{in}-}\right| =1.5\,\mathrm V$ are illustrated in Fig. 4. The output voltage $V_\mathrm{out}$ is stable at $1.15\;{\text{V}}$ ($V_{\mathrm{in}+}-V_T$) or $-1.15\,\mathrm V$ ($V_{\mathrm{in}-}+V_T$) with a transient learning process as the dotted box. The results indicate that $V_{\mathrm{in}+}$ and $V_{\mathrm{in}-}$ can be used as learning voltages because the two memristors are in reverse parallel, and memristances $M_a$ and $M_b$ will vary until the target voltage is achieved. Thereafter, memristance $M_a$ and $M_b$ become stable and are used as learning weights.

Fig. 4

Simulation results of the memristor-based learning circuit with different pulse inputs. a Case 1: learning process under positive voltage, b case 2: learning process under negative voltage

The learning time $T_L$ is an important parameter influencing the performance of the proposed learning circuit. $T_L$ is related to the amplitude of the input pulse $V_\mathrm{in}$ and depends on the initial values of the two memristors $M_{ao}$ and $M_{bo}$. $M_{ab}$ gradually decreases during the learning process, and the maximum learning time $T_\mathrm{Lmax}$ is obtained when the initial memristor $M_{ao}=M_{bo}=R_\mathrm{off}$. The final resistance value $M_{ab}$ obtained by learning satisfies $R_\mathrm{on}<M_{ab}<R_\mathrm{off}$. Thus, the maximum learning time satisfies $T_\mathrm{Lmax} < T_\mathrm{ON}$ as illustrated in Fig. 4. The learning time $T_L=0.084\,\mathrm ms$ (Fig. 4a, b) is less than $T_\mathrm{ON}=0.11\,\mathrm ms$ (Fig. 3a). The width of the input pulse is larger than $T_\mathrm{ON}$ to guarantee the learning time.

3 Design of basic logic gate

In this section, a universal memristive circuit analogous to the neural network of a logic family is proposed. In our circuit, the memristor-based learning block is proposed to learn the weights that are then used to complete the AND, OR, NOR, NAND, and XOR operations without initialization.

3.1 Memristor-based perception-like logic circuit

Fig. 5

A universal memristor-based logic circuit that implements AND, OR, NAND and NOR logic functions using memristor learning circuit block

The proposed memristor-based logic circuit shown in Fig. 5 consists of three parts: a sum block, a learning block, and a compare block. The voltage relationships between the sum and learning parts are calculated as follows:

$$\begin{aligned} V_\mathrm{add}&=-k\times (V_A+V_B), \end{aligned}$$

(8)

$$\begin{aligned} V_R&=V_\mathrm{add}\times \frac{R}{(M_a//M_b)+R}, \end{aligned}$$

(9)

where $k={R_A}/{R_n}$. $V_A$ and $V_B$ are input voltages serving as logic values and $1\,\mathrm V$ and $-1\,\mathrm V$ represent the logic states ‘1’ and logic ‘0,’ respectively. $R_A$ and $R_N$ are the resistances of two resistors adjusting the output voltage of the sum block $V_\mathrm{add}$. $V_R$ is the output voltage of the memristor-based learning block.

Table 1 The comparison unit for boolean logic operation when $V_{Tp}=1.8\,\mathrm{V}, V_{Tn}=-1.8\,\mathrm{V}$, $V_a=1$ and $V_b=-1$

The work procedures of the sum and learning blocks are discussed under the following situations.

• (i) If either of the two input logic states is ‘0’ and the other is ‘1,’ which indicates that either $V_A$ or $V_B$ is 1, and the other is $-1$, then, $V_\mathrm{add}=0$. Thus, no current flows through the circuit, and the output voltage of the learning block is $V_{R}=0$.

• (ii) If both input logic states are ‘1,’ which indicates that $V_A$ and $V_B$ are both 1, then, $V_\mathrm{add}=-2k$, and the output voltage of the learning block is $V_{R}=-2k+V_T$.

• (iii) If both input logic states are ‘0,’ which indicates that $V_A$ and $V_B$ are both $-1$, then, $V_\mathrm{add}=2k$, and the output voltage of the learning block is $V_{R}=2k-V_T$.

According to the above analysis, the output voltage of the learning block is $V_{R}={(0, -2k+ V_T, 2k-V_T)}$ and can be adjusted by choosing the appropriate resistors (i.e., $R_A$ and $R_N$) to regulate k. Let $k=0.75$, $V_T=0.35$, $V_a=1$, and $V_b=-1$. The threshold voltages of PMOS and NMOS are $V_{Tp}=1.8\,\mathrm{V}$ and $V_{Tn}=-1.8\,\mathrm{V}$, respectively. Then, different logical operations can be achieved by selecting various comparison units, as summarized in Table 1. The calculation processes are analyzed as follows: When $M_{os1}$ is PMOS and $M_{os2}$ is NMOS. Only when both input logic states are ‘1’ does $V_R=-2k+V_T=-1.15$ become lower than $V_{TB}=-0.8$; thus, $V_{o1}$ is 1, which indicates that the output logic is ’1.’ Otherwise, $V_R~(0$ or $2k-V_T=1.15)$ is always higher than $V_{TB}=-0.8$, and $V_{o1}$ is $-1$, which indicates that the output logic is ‘0.’ In this case, the circuit output $V_{o1}$ can complete the AND operation. The NAND operation can be obtained by performing a NOT operation to the AND logic, which can be achieved by adding an NMOS to the input $V_{o1}$, thereby enabling the circuit to calculate the NAND logic for output $V_{o2}$. Similarly, when $M_{os1}$ is NMOS and $M_{os2}$ is PMOS, the circuit can complete the OR and NOR operations. Given that the XOR operation is nonlinearly separable, we can use there MOSFETs shown in Table 1 to complete the XOR operation. Different Boolean logical operations can be achieved by combining the selected MOSFETs in a unit circuit, as demonstrated in Fig. 5.

3.2 PSpice simulation results

We simulate the aforementioned circuits using the cadence PSpice simulation environment with the memristor model. The $V_A$ and $V_B$ are input pulse sources and can generate random timing logic signals. The circuit parameters are $R_A=0.75\,\mathrm{k}\Omega$, $R_n=1\,\mathrm{k}\Omega$, $k=R_A/R_n=0.75$, $R=0.1\,\mathrm{k}\Omega$, $R_f=1\,\mathrm{k}\Omega$, $V_a=1\,\mathrm{V}$ and $V_b=-1\,\mathrm{V}$. The initial memristance values are$M_{a0}\!=400\,\Omega$ and $M_{b0}=300\,\Omega$. The used operational amplifier is LM741, and the supply voltage is $\pm 10\,\mathrm V$. The PMOS and NMOS chips are M2S136 and M2SK1029. Note that the proposed circuit does not have to be initialized, and the initial values $M_{a0}$ and $M_{b0}$ are random and discretionary.

When $M_{os1}$ and $M_{os2}$ are PMOS and NMOS, the circuit functions as the AND and NAND gates. The Pspice simulation results of the AND and NAND gates are shown in Fig. 6a. The stages in the dotted box of Fig. 6 are learning stages, the voltage across the learning block $V_M$ is higher or lower than the positive or negative threshold voltage, and the memristance is changed in the learning stages. Once the learning process is completed, the circuit achieves a steady state, and the memristance values of two memristors $M_a$ and $M_b$ are invariant. A detailed explanation of the learning block is found in Sect. 2. Various combinations of logic inputs, such as $1 \cdot 1=1$ and $0 \cdot 1=0$, are tested after the learning stage, and the simulation results demonstrate that the circuit output $V_{o1}$ can accurately calculate the AND logic gates after the learning stage. The results of NAND logic calculations can be obtained from $V_{o2}$. Logical OR and NOR operations are also verified by simulations, and the corresponding results are presented in Fig. 6b. The dotted boxes in Fig. 6 are the learning stages, and the learning time $T_L\approx 0.045\,\mathrm ms$, which is lower than $T_\mathrm{ON}=0.11\,\mathrm ms$. These simulation results verify that the proposed memristor-based perception-like logic circuit exhibits self-learning and logical operation after learning.

Fig. 6

Basic Boolean logic simulation results. a AND and NAND gate, b OR gate and NOR gate

3.3 Device variability effect analysis

In this subsection, possible circuit device changes are explored, and their effects on the logic operation are analyzed. The explored circuit devices include operational amplifiers, memristors, and MOSFETs, which affect the output of the logic circuit. First, the operational amplifier performed as a sum operation affects $V_\mathrm{add}$. The actual circuit output $V_\mathrm{add}$ will more or less deviate from the theoretical values calculated in Eq. (8). Second, the output $V_R$ is affected by the voltage terminal of the memristor $V_M$. The actual voltage $V_M$ continues to make small changes when the voltage across the memristor is close or equal to the threshold $V_T$. Finally, MOSFETs exhibit variations in comparison voltage $V_{TB}$.

The influence of the logic operation for different $V_\mathrm{add}$ and $V_M$ is presented in Fig. 7. $V_M$ varying between 0.2 ($-0.2$) and 0.45 ($-0.45$) simulates the actual terminal voltage variation considering the fluctuations of a real memristor, and the threshold voltage is $V_T=0.35$. $V_\mathrm{add}$ varying between 1.2 ($-1.2$) and 1.8 ($-1.8$) simulates the voltage fluctuation obtained from the operational amplifier wherein the theoretical output is 1.5. Figure 7a, b shows the results of changing $V_\mathrm{add}$ and $V_M$ for (-1,-1) and (1,1) inputs, respectively. In Fig. 7, $V_R$ is the dynamic output voltage of the learning circuit which synthesizes two variation factors $V_M$ and $V_\mathrm{add}$. The logic output is determined by the comparison between voltage $V_R$ and $V_{TB}$. The learning output $V_R$ displayed in Fig. 7a exceeds the comparison voltage $V_{TB}$, while $V_R$ (Fig. 7b) under the comparison voltage $V_{TB}$ is the correct logic output. The simulation results indicate that the circuit can perform the correct logic operation except in the case of the dashed box. Figure 7a illustrates that a failure logic occurs only when $V_\mathrm{add}=1.2$ and $V_{M}>0.4$. Whether $V_\mathrm{add}=1.2$ or $V_{M}>0.4$ presents an extreme hypothetical situation because these values are hard to happen in the real circuit. Thus, the circuit can perform the correct logic operation given different device changes of the actual circuit. The permissible variations of $V_{M}$ is shown in Fig. 8 when $V_{R}$ is changed by $\pm 20\%$. The device variations of the memristor and operational amplifier are comprehensively considered, and $V_{R}$ is assumed to change by $\pm 20\%$. The results indicate that $V_{TB}$ and $V_{R}$ can still be correctly distinguished. The permissible variation $\Delta V_{TB}$= $15\%$ when the assumed variation $\Delta V_{R}$= $20\%$. These results indicate that the proposed circuit shows high robustness and immunity to device variability.

Fig. 7

Influence of the changes of $V_{M}$ and $V_\mathrm{add}$ on the logic operation. a ($-1,-1$) input case, b (1,1) input case

Fig. 8

The permissible variation $V_{TB}$ to change $V_{R}$ by $\pm 20\%$. a ($-1,-1$) input case, b (1,1) input case

4 Design of complex logic gate

Additional logic functions can be added to the basic logic family for the sake of generality using the same design principles described in Sect. 3.

4.1 Design of a multi-fan-in logic circuit

The design of a multi-fan-in logic circuit is shown in Fig. 9; here, the two inputs are transformed into multi-inputs. The sum block can be calculated as follows:

$$\begin{aligned} V_\mathrm{add}=-k_n\times (V_A+V_B+\cdots V_N), \end{aligned}$$

(10)

where $k_n\!=\!\frac{R_B}{R_n}$. Let $R_B=\frac{2}{n}R_A$, then $k_n=\frac{2}{n}k$. The proposed circuit can complete the multi-fan-in AND, NAND, OR, and NOR logic operations with different combinations of [$M_{os1}$, $M_{os2}$]. Output logic ‘1’ only occurs when all inputs are logic ‘1’ in the multi-fan-in AND logic. The sum of the input $V_\mathrm{add}$ is the minimum value $-nk_n=-2k$ when all inputs are logic ’1’, which is identical to the basic AND logic. Analogously, the sum of the input $V_\mathrm{add}$ is the maximum value $nk_n=2k$ when all inputs are logic ’-1’, which is identical to the basic OR logic. Taking these relations into consideration, the subsequent selection operation is consistent with the basic logic circuit, as shown in Table 1. Figure 10 shows the simulation results of four-input OR and AND operations. The circuit parameters are identical to those of the basic logic gate, except for $R_B=\frac{2}{n}R_A=0.75\,\mathrm{k}\Omega$.

Fig. 9

Schematic of multi-fan in logic circuit

Fig. 10

Simulation results of four-fan logic circuit. a Four-fan in AND gate, b four-fan in OR gate

4.2 Design of the implication logic

For the implication logic family, the modified circuit shown in Fig. 11 is proposed to operate implication (IMP, $f=A+\bar{B}$), converse implication (CIMP, $f=\bar{A}+B$), nonimplication (NIMP, $f=A\cdot \bar{B}$), and converse nonimplication (CNIMP, $f=\bar{A}.B$).

As shown in Fig. 11, inverse sums are converted into addition operations consisting of switches $S_+$, $S_-$. The circuit can achieve different IMPLY logic operations by selecting various combinations of switches $S_+$, $S_-$. For example, the two input voltages represent A and $\bar{B}$ if $V_A$ and $V_B$ connect to $S_+$ and $S_-$, respectively. The Sum block can be calculated as follows:

$$\begin{aligned} V_\mathrm{add}=-k\times (V_A-V_B), \end{aligned}$$

(11)

where $k={R_A}/{R_n}$. According to the basic logic family circuit proposed in Sect. 3, all logic operations of the IMPLY logic family can be obtained by choosing diverse combinations of switches $S_+$, $S_-$ and MOSFETs $M_{os1}$ and $M_{os2}$, which are listed in Table 2. Some of these logic operations are verified in the proposed circuit by PSpice simulation. The circuit parameters are identical to those of the basic logic gate, and the results are depicted in Fig. 12; here, the learning processes are conducted before the logic calculation.

Fig. 11

Schematic of implication logic circuit

Table 2 The states of $S_+$, $S_-$, M$_{os1}$ and M$_{os2}$ for IMPLY logic operation

Fig. 12

Simulation results of part of the implication logic circuit. a ${\ A\cdot \bar{B}}$ and $\overline{\ A\cdot \bar{B}}$, b $A+\bar{B}$ and $\overline{A+\bar{B}}$

4.3 Design of arbitrary logic

Considering that the proposed circuit structures analyzed in Sects. 3, 4.1 and 4.2 can complete basic logic operations, such as Boolean, IMPLY, and multi-fan-in logic, extending the circuit to perform arbitrary logic operations is rational. An arbitrary logic circuit is proposed in Fig. 13.

As previously analyzed, selecting switches $S_A,S_B,\cdots ,S_N$ in the multi-fan-in sum block to $S_+$ or $S_-$ can produce the corresponding $V_\mathrm{in}$ or $\overline{V_\mathrm{in}}$. Moreover, selecting output $V_{o1}$ or $V_{o2}$ in the compare block can produce the corresponding $V_\mathrm{out}$ or $\overline{V_\mathrm{out}}$. The AND or OR logic operation can be decided by choosing different combinations of $M_{os1}$ and $M_{os2}$. Taking these concepts into consideration, the arbitrary logic can be achieved with different combinations of $S_+$, $S_-$, $M_{os1}$ and $M_{os2}$. Take a four-input logic as an example. A combinational logic $A\cdot \bar{B}\cdot C\cdot \bar{D}$ and $A+\bar{B}+C+\bar{D}$ is performed with the combinational switch operation ${(V_A,V_C)\rightarrow S_+}$, $(V_B,V_D)\rightarrow S_-$, $S \rightarrow S_2$. The sum block can be calculated as

$$\begin{aligned} V_\mathrm{add}=-k_n\times (V_A-V_B+V_C-V_D), \end{aligned}$$

(12)

where $k_n={R_B}/{R_n}$. For a four-input logic, let $R_B=\frac{2}{4}R_A$, then $k_n=\frac{2}{4}k$. The operations in the compare block are consistent with the basic logic gate. The simulation results of the combinational logic are shown in Fig. 14; here, the learning processes are conducted before the logic calculation. The circuit parameters are identical to those of the basic logic gate.

Fig. 13

Schematic of arbitrary logic circuit

Fig. 14

Simulation results of arbitrary four-fan in logic. a ${A+\bar{B}+C+\bar{D}}$ and $\overline{A+\bar{B}+C+\bar{D}}$, b ${A\cdot \bar{B}\cdot C \cdot \bar{D}}$ and $\overline{A\cdot \bar{B}\cdot C \cdot \bar{D}}$

4.4 Comparisons between the memristor logic circuits

In this section, a detailed comparison between the proposed and existing memristor-based logic circuits is presented. A comprehensive comparison of different memristive logic circuits is listed in Table 3.

Compared with the existing logic circuits, the proposed self-learning logic circuit offers a uniform standardized block that can be configured with programmable switches in the sum and compare blocks. Taking advantage of such a design, different logic gates can be achieved in a uniform circuit. The logic operation in the proposed circuits is relatively simple and does not require set/reset/input initialization operations. A cascade connection can also be achieved given that the input and output are voltage signals. In contrast to traditional memristor logic circuits designed with high and low resistance states, the proposed memristor logic circuit can provide arbitrary resistance values, such as memristive weights, which are automatically be obtained by self-learning.

Table 3 Comparison of various memristor-based logic circuit

Table 4 Hardware comparison

A comparison of the hardware required by different memristive circuits is given in Table 4; here, the drivers provide signals for initialization. As shown in the table, the hardware required in this work is relatively larger than that needed for other memristor-based logic circuits. The main hardware requirement is reflected in the sum block, which contains operational amplifiers. At present, the sum block is a universal circuit module, and studies of this block are relatively mature. Thus, designing a simpler sum circuit to optimize the consumption of the proposed circuits is recommended for future studies. However, the proposed logic shows excellent responses as the number of inputs increases. A large number of inputs are practicable for the proposed circuit given that it is a module-based unified one. In contrast to the existing technologies that are practically limited to approximately 2–10 inputs per gate, the proposed logic circuit presents a simpler design and layout of large variable digital circuits.

Table 5 shows a comparison of the latencies of different circuits. As shown in the table, the work presented has a minimum possible latency of a 1-step operation. The latencies are given in terms of the number of steps necessary to complete one logic calculation. For example, a hybrid CMOS step is a gate delay, whereas IMPLY, MAGIC, MAD, and MSLL are the applications of a drive signal. However, this delay does not include the set/reset/input initialization cycles, as required in other works. The initialize operation is an essential one in existing logic circuits. Arbitrary logic can be achieved without initialization in the proposed circuit, which means fast operating times.

Table 5 Latency comparison

Table 6 Truth table of 8-of-3 encoder

5 Design of encoder and decoder based on memristor logic

The proposed self-learning logic circuit is used for calculating various multi-fan-in logic operations. The circuit can be applied to different types of digital computations according to this logic. In this section, an 8-of-3 encoder and a 3-of-8 decoder based on the proposed logic circuit are presented. In particular, the encoder and decoder proposed in this paper are aimed at digital system, which can be implemented by combinatorial logic circuit. An arbitrary number of encoders and decoders can also be achieved with the same layout mechanism using the universal logic circuit design.

5.1 Design of an 8-of-3 encoder

The main function of an encoder is to convert a specific meaning of information into binary code. The truth table of an 8-of-3 encoder is shown in Table 6. The input signal $x_i$ represents a set of variables with different information. Only one of the inputs $x_0$–$x_7$ is logic ‘1’ in every input series. The outputs are three-digit binary codes ABC. Each input $x_i$ corresponds to a unique set of coded signals ABC.

According to the truth table, we can obtain the relational expression:

$$\begin{aligned} \left\{ \begin{matrix} A=x_1+x_3+x_5+x_7&{}\\ B=x_2+x_3+x_6+x_7&{}\\ C=x_4+x_5+x_6+x_7.&{} \end{matrix}\right. \end{aligned}$$

(13)

Fig. 15

The schematic of 8-of-3 encoder

where ABC is the expression of four OR operations. The multi-fan-in OR gates are used to complete the coding process. The complete circuit of the 8-of-3 encoder is designed and shown in Fig. 15. The designed circuit consists of three 8-input OR gate logic. A programmable memristor array is used to perform the ADD operation, in which the memristance variables $R_\mathrm{on}$ and $R_\mathrm{off}$ are used as selection switches. For example, in the sub-circuit of the logic output $V_A$, $M_{11}=M_{13}=M_{15}=M_{17}=R_\mathrm{on}$ and $M_{10}=M_{12}=M_{14}=M_{16}=R_\mathrm{off}$.

The simulation result is shown in Fig. 16. The input voltage $x_i$ is 1V. $V_A$, $V_B$ and $V_C$ are output voltages serving as logic values and $4\,\mathrm V$ and $-4\,\mathrm V$ represent the logic states ‘1’ and logic ‘0,’ respectively. As shown in the figure, when $x_1$=1V, the out logic is ‘001’, when $x_4$=1V, the out logic is ‘100’. By analogy, all coding operation can be accurately achieved after learning.

Fig. 16

The simulation result of 8-of-3 encoder. a Input logic voltages, b output logic voltages

5.2 Design of a 3-of-8 decoder

Decoding is the reverse process of coding, which converts binary codes with specific meanings into corresponding output signals. The truth table of a 3-of-8 decoder is shown in Table 7. The inputs are three-digit binary codes $A_2A_1A_0$. The output signal $V_i$ represents the corresponding decoded result. Only one of the outputs $V_0$ -$V_7$ is logic ‘1’ in every input series. Each three-digit binary code $A_2A_1A_0$ corresponds to an output signal $V_i$.

Table 7 Truth table of 3-of-8 decoder

According to the truth table, we can obtain the relational expression

$$\begin{aligned} \left\{ \begin{matrix} V_0=\bar{A}_2 \bar{A}_1 \bar{A}_0=m_0&{}V_1=\bar{A}_2 \bar{A}_1 A_0=m_1\\ V_2=\bar{A}_2 A_1 \bar{A}_0=m_2&{}V_3=\bar{A}_2 A_1 A_0=m_3\\ V_4= A_2 \bar{A}_1 \bar{A}_0=m_4&{}V_5= A_2 \bar{A}_1 A_0=m_5\\ V_6= A_2 A_1 \bar{A}_0=m_6&{}V_7= A_2 A_1 A_0=m_7.\\ \end{matrix}\right. \end{aligned}$$

(14)

where $V_0$–$V_7$ is the expression of three AND operations. We can use the multi-fan-in ADD gates shown in Fig. 17 to complete the decoding process. The memristor array is used as a switch to select $A_i$ or $\overline{ A_i}$. For example, in the sub-circuit of the output $V_0$, $M_{10}=M_{20}=M_{30}=R_\mathrm{off}$ and $M_{1'0}=M_{2'0}=M_{3'0}=R_\mathrm{on}$.

The simulation result is shown in Fig. 18. The input voltages $A_0$, $A_1$ and $A_2$ are $1\,\mathrm V$ serving as logic states ‘1’ and $\bar{A}_0$, $\bar{A}_1$ and $\bar{A}_2$ are $-1\,\mathrm V$ represent the logic states ‘0’. The output voltage $V_i$ is 4V. As shown in the figure, when input logic is ‘010’, the out $V_2$ is 4V, when input logic is ‘011’, the out $V_3$ is 4V. By analogy, all decoding operation can be accurately achieved after learning.

Fig. 17

The schematic of 3-of-8 decoder

Fig. 18

The simulation result of 3-of-8 decoder. a Input logic voltages, b output logic voltages

6 Conclusion

In this work, a universal logic circuit based on memristors is designed, which perform various types of logic, including Boolean, IMPLY, and random logical combinations. Based on the continuous adjustable feature of memristors, a self-learning method is proposed to solve the initialization problem of existing designs. Compared to previous solutions, our design is a more versatile method and speeds up computing. Furthermore, the proposed circuit can easily be extended to multi-fan-in logic and cascade connections. The designed circuit can be used to build large-scale encoder and decoder, which will be well applied in the future digital field. A disadvantage of the proposed design, however, is that it presents increased hardware requirements compared with that needed by previously published solutions. Therefore, further optimization of the design and applications of the proposed circuit is recommended in future studies.