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A systematic EHW approach to the evolutionary design of sequential circuits

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Abstract

The main difficulty in the evolutionary design of finite state machines (FSMs) is lack of effective systematic EHW approach. To accomplish the evolutionary design of FSMs, a systematic EHW method named genetic programming–evolutionary strategy (GP–ES), which is a combination of ES and GP, is proposed. ES optimizes the state assignment and provide them to GP for population generation; GP is responsible for evolving the combinational part of FSM, and feeding the fitness of population back to ES for the evaluation of corresponding state assignments. GP–ES is tested extensively on twenty FSMs from MCNC Library. The results demonstrate that the GP–ES-derived state assignments are more efficient than the ones of Xia, Ali, Almaini and NOVA in the evolutionary design of FSMs. The results also illustrate that the GP–ES is superior to conventional synthesis tools in terms of complexity reduction for the design of small and middle FSMs. GP–ES also performs well in comparison with 3SD-ES in most cases.

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References

  • Aiman HEl-M, Ahmad TS, Sadiq MS (2013) Binary particle swarm optimization (BPSO) based state assignment for area minimization of sequential circuits. Appl Soft Comput 13:4832–4840

    Article  Google Scholar 

  • Ali B, Almaini AEA, Kalganova T (2004) Evolutionary algorithms and their use in the design of sequential logic circuits. Genet Program Evolv Mach 5:11–29

    Article  Google Scholar 

  • Almaini AEA, Miller JF, Thomson P (1995) State assignment of finite state machines using a genetic algorithm. IEE Proc Comput Digit Tech 142(2):279–286

    Article  Google Scholar 

  • Amaral JN, Tumer K, Ghosh J (1995) Designing genetic algorithms for the state assignment problem. IEEE Trans Syst Man Cybern 25(4):100–108

    Article  Google Scholar 

  • Berkeley (1992) Electronics research laboratory, SIS: a system for sequential circuit synthesis, Release 1992.05. http://www.eecs.berkeley.edu/Pubs/TechRpts/1992/ERL-92-41.pdf

  • Berkeley (2011) Logic synthesis and verification group, ABC: a system for sequential synthesis and verification, Release 2011.02. http://www.eecs.berkeley.edu/~alanmi/abc

  • Chuang CH, Lin CL, Chang YC (2013) Design of synthetic biological logic circuits based on evolutionary algorithm. IET Syst Biol 7(4):89–105

    Article  Google Scholar 

  • Coello CAC, Luna EH, Aguirre AH (2003) Use of particle swarm optimization to design combinational logic circuits. In: Proceedings of ICES 2003, LNCS 2606, pp 398–409

  • Daneshfar F, Maihami V (2014) Distributed learning algorithm applications to the scheduling of wireless sensor networks. Theory Practic Appl IGI Glob Handb Res Novel Soft Comput Intell Algorithms, pp 860–891. doi:10.4018/978-1-4666-4450-2

  • Garvie M, Thompson A (2003) Evolution of self-diagnosing hardware. In: Proceedings of international conference on evolvable systems: from biology to hardware (ICES2003), 17–20 March. Trondheim, Norway, pp 238–248

  • Gordon TGW, Bentley PJ (2005) Development brings scalability to hardware evolution. In: Proceedings of the 2005 NASA/DoD conference of evolution hardware. 29 June–1 July, Washington DC, USA, pp 272–279

  • Jassani BAAL (2011) State assignment for sequential circuits using multi-objective genetic algorithm. IET Comput Digit Techn 5(4):296–305

    Article  Google Scholar 

  • Kung CK, Liu FT, Chen YJ (2010) Logic circuit design by neural network and PSO algorithm. In: Proceedings of the 1-st international conference on pervasive computing signal processing and applications (PCSPA), pp 456–459

  • Liang HJ, Luo WJ, Wang XF (2009) A three-step decomposition method for the evolutionary design of sequential logic circuits. Genet Program Evolv Mach 10:231–262

    Article  Google Scholar 

  • Lücken C, Barán B, Brizuela C (2014) A survey on multi-objective evolutionary algorithms for many-objective problems. Comput Optim Appl 58:707–756

    MATH  MathSciNet  Google Scholar 

  • Manfrini F (2014) Optimization of combinational logic circuits through decomposition of truth table and evolution of sub-circuits. In: Proceedings of 2014 IEEE congress on evolutionary computation (CEC), pp 945–950

  • Miller JF, Thomson P (2000) Cartesian genetic programming. In: Proceedings of Europe Genetic Programming, pp 121–132

  • Miller JF, Job D, Vassilev VK (2000) Principles in the evolutionary design of digital circuits-PartI. J Genet Program Evolv Mach 01:8–35

    MATH  Google Scholar 

  • Pauline C, Tyrrell HaddowAndy M (2011) Challenges of evolvable hardware: past, present and the path to a promising future. Genet Program Evol Mach 12:183–215

  • Saeidinezhad H (2012) Reversible circuit optimization using PSO algorithm. In: Proceedings of international conference on computer science, engineering and technology (ICCSET)

  • Santini CC, Amaral JFM, Pacheco MAC (2004) Evolvability and reconfigurability. In: Proceedings of 2004 IEEE international conference on field programmable technology, pp 105–122

  • Sekanina L, Vasicek Z (2012) A SAT-based fitness function for evolutionary optimization of polymorphic circuits. In: Proceedings of 2012 design, automation and test in Europe conference and exhibition (DATE), pp 715–720

  • Sekanina L, Vasicek Z (2013) Approximate circuit design by means of evolvable hardware. In: Proceedings of 2013 IEEE international conference on evolvable systems (ICES), pp 21–28

  • Shanthi AP, Singaram LK, Parthasarathi R (2005) Evolution of asynchronous sequential circuits. In: Proceedings of the 2005 NASA/DoD conference of evolution hardware. pp 238–248

  • Shanthi AP, Parthasarathi R (2009) Practical and scalable evolution of digital circuits. Appl Soft Comput 9:618–624

    Article  Google Scholar 

  • Stomeo E, Kalganova T (2004) Improving EHW performance introducing a new decomposition strategy. In: Proceedings of the 2004 IEEE conference on cybernetics and intelligent systems, pp 439–444

  • Stomeo E, Kalganova T, Lambert C (2006) Generalized disjunction decomposition for the evolution of programmable logic array structures. In: Proceedings of the 1-st NASA/ESA conference on adaptive hardware and systems (AHS’06), pp 179–185

  • Tao Y, Zhang Y, Cao J (2013) A module-level three-stage approach to the evolutionary design of sequential logic circuits. Genet Program Evolv Mach 14(2):191–219

    Article  Google Scholar 

  • Tao Y, Cao J, Zhang Y (2012) Using module-level evolvable hardware approach in design of sequential logic circuits. In: Proceedings of 2012 IEEE world congress on computational intelligence, pp 1604–1611

  • Tao Y, Zhang Y, Zhang L (2015) A Projection-based decomposition for the scalability of evolvable hardware. Soft Comput. doi:10.1007/s00500-015-1636-2 (Online)

  • Vasicek Z, Sekanina L (2014) Evolutionary approach to approximate digital circuits design. IEEE Trans Evolut Comput 19(3):432–444

  • Vasicek Z, Sekanina L (2011) Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware. Genet Program Evolv Mach 12(3):305–327

    Article  Google Scholar 

  • Villa T, Alberto Sangiovanni-Vincentelli (1990) NOVA: state assignment of finite state machines for optimal two-level logic implementation. IEEE Trans Comput Aided Des Integr Circuits Syst 9(9):905–924

    Article  Google Scholar 

  • Voropai NI, Gamm AZ, Glazunova AM (2012) Application of meta-heuristic optimization algorithms in electric power systems. Innov Power Control Optim Emerg Energy Technol IGI Glob, pp 564–615. doi:10.4018/978-1-61350-138-2

  • Xia Y, Almaini AEA (2002) Genetic algorithm based state assignment for power and area optimisation. IEE Proc Comput Digit Tech 149(4):128–133

    Article  Google Scholar 

  • Yang S (1991) Logic synthesis and optimization benchmarks. Version 3.0. Tech Report. Microelectronics Center of North Carolina

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Acknowledgments

This research is supported by the Natural Science Foundation of the Jiangsu Higher Education Institutions of China (Grant No. 13KJB520023), the National Science Fund of China (Grant No. 61272105, 61401281) and scientific research project of Soochow University (Grant No. SD2013A16).

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Correspondence to Yuzhen Zhang.

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Communicated by V. Loia.

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Tao, Y., Zhang, Q., Zhang, L. et al. A systematic EHW approach to the evolutionary design of sequential circuits. Soft Comput 20, 5025–5038 (2016). https://doi.org/10.1007/s00500-015-1791-5

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