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Performance estimation of junctionless field effect diode

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Abstract

For the first time in this study a junctionless field effect diode (JL-FED) is proposed and investigated using 2D simulations. In this structure, the advantages of junctionless field effect transistor (JL-FET) and FED are combined together. Unlike a FED, a JL-FED device can be turned on without applied biases to the control gates. JL-FED device with channel lengths less than 15 nm could not be turned off due to the short channel effects (SCEs). We have proposed a new structure, namely modified JL-FED (MJ-FED), to reduce the issues of SCEs. All structural parameters of MJL-FED device are quite the same as the JL-FED device, except its control gates work function. Our simulation results demonstrate that OFF-state current of MJL-FED with 10 nm channel length is approximately six orders of magnitude lower than that of JL-FED. Moreover, simulation results obtained here show that the MJL-FED with 22 nm channel length exhibit ION/IOFF ratio of ~ 3 × 1014 and a subthreshold swing (SS) of ~ 78 mV/decade, which are considerably improved as compared to those of reported so far in the literature. As a result, MJL-FED is a promising candidate for a switching performance.

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  1. Department of Electrical Engineering, Abhar Branch, Islamic Azad University, Abhar, Iran

    Mahdi Vadizadeh

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Vadizadeh, M. Performance estimation of junctionless field effect diode. Appl. Phys. A 125, 495 (2019). https://doi.org/10.1007/s00339-019-2788-1

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