Abstract
Meeting due dates for delivery of products is a key factor in achieving customer satisfaction in today’s globally competitive semiconductor market. However, undesirable production variations are inevitable in this industry, especially for ‘back-end’ factories that are closer to customers. This makes it difficult for management to maintain (or improve) a factory’s performance with respect to delivery on due dates. In practice, production managers ameliorate the adverse effects of manufacturing uncertainties by control of work in progress (WIP). The present study therefore proposes a WIP-exception management model to define, detect, and respond to WIP exceptions. First, a model for determining acceptable WIP deviation levels (AWDLs) is established to assist production managers in identifying WIP exceptions on monitored workstations. A correction mechanism is then proposed to adjust deviations in WIP levels (‘WIP exceptions’) in accordance with the projected AWDLs as soon as possible. A simulation model is constructed, and experiments are then conducted to evaluate the proposed model. The proposed model is confirmed as being able to set appropriate and effective WIP-exception conditions to trigger correction actions. The simulation experiment also demonstrates that the WIP-correction action can shorten the ‘back-to-normal’ duration, prolong the time between successive WIP exceptions, and improve average on-time delivery percentage. The study concludes that the proposed model does determine effective exception-triggering conditions, rectifies abnormal WIP levels promptly, and results in improved performance on due-date delivery for semiconductor ‘back-end’ factories.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Askin RG, Krisht AH (1994) Optimal operation of manufacturing systems with controlled work-in-process levels. Int J Prod Econ 37(2):1637–1653
Burman DY, Gurrola-Gal FJ, Nozari A, Sathaye S, Sitarik JP (1986) Performance analysis techniques for IC manufacturing lines. ATT Tech J 65(4):46–57
Buzacott JA (1971) The role of banks in flow-line production systems. Int J Prod Res 9(4):425–436
Chen H, Harrison JM, Mandelbaum A, Wein LM (1998) Empirical evaluation of a queueing network model for semiconductor wafer fabrication. Oper Res 36(2) March-April
Chen HC, Lee CE (2003) Pull systems for control and dummy wafers. Int J Adv Manuf Technol 22:805–818
Goldratt EM (1990) Theory of constraints and how should it be implemented? North River Press, New York
Gross D, Harris CM (1974) Fundamentals of queueing theory. Wiley, New York, USA
Hopp WJ, Roof ML (1998) Setting WIP levels with statistical throughput control (STC) in CONWIP production lines. Int J Prod Res 36(4):867–882
Huang CL, Huang YH, Chang TY, Chang SH, Chung CH, Huang DT, Li RJ (1999) The construction of production performance prediction system for semiconductor manufacturing with artificial neural networks. Int J Prod Res 37(6):1387–1402
Kim JS, Leachman RC (1994) Decomposition method application to a large scale linear programming WIP projection model. Eur J Oper Res 74:152–160
Lee YH, Lee BK, Jeong B (2000) Multi-objective production scheduling of probe process in semiconductor manufacturing. Prod Plan Control 11(7):660–669
Lee CY, Martin-Vega LA, Uszoy R, Hinchman J (1993) Implementation of a decision supporting for scheduling semiconductor test operations. J Electron Manuf 3:121–131
Li S, Tang T, Collins DW (1996) Minimum inventory dispatching in semiconductor wafer fabrication. IEEE Trans Semicond Manuf 9(1):145–149
Lin YH, Lee CE (2001) A total standard WIP estimation method for wafer fabrication. Eur J Oper Res 131:78–94
Manzione LT (1990) Plastic packaging of microelectronic devices. Technical Report, AT&T Bell Laboratories
Miller DJ (1990) Simulation of a semiconductor manufacturing line. Commun ACM 33(10):99–108
Montgomery DC (2001) Design and analysis of experiments, 5th edn. Wiley, New York
Robinson JK, Fowler J, Bard J (1995) The use of upstream and downstream information in scheduling semiconductor batch operations. Int J Prod Res 7:1849–1870
Rose O (1998) WIP evaluation of a semiconductor factory after bottleneck workcenter breakdown. Proceedings of the 1998 Winter Simulation Conference, IEEE, Piscataway, NJ, 997–1003
Sivakumar AI, Chong CS (2001) A simulation based analysis of cycle time and throughput in semiconductor backend manufacturing. Comput Ind 45:59–78
Tu et al (2005) Model to determine the backup capacity of a wafer foundry. Int J Prod Res 43(2):339–359
Tu YM, Li RL (1998) Constraint time buffer determination model. Int J Prod Res 36(4):1091–1130
Uszoy R, Church IA, Ovacik I, Hinchman J (1993) Performance evaluation of dispatching rules for semiconductor testing operations. J Electron Manuf 3:95–105
Uzsoy R, Lee CY, Martin-Vega LA (1992) A review of production planning and scheduling models in the semiconductor industry part I: system characteristics, performance evaluation and production planning. IIE Trans 24(4):47–60
Wein LM (1988) Scheduling semiconductor wafer fabrication. IEEE Trans Semicond Manuf 1(3):115–130
Wein LM (1992) On the relationship between yield and cycle time in semiconductor wafer fabrication. IEEE Trans Semicond Manuf 5(2):156–158
Wiendahl H (1995) Load-oriented manufacturing control. Springer, Berlin Heidelberg New York
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Guo, RS., Chiang, D.M. & Pai, FY. A WIP-based exception-management model for integrated circuit back-end production processes. Int J Adv Manuf Technol 33, 1263–1274 (2007). https://doi.org/10.1007/s00170-006-0559-6
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00170-006-0559-6