Skip to main content
SpringerLink
Log in

A CORDIC-Based Low-Power Statistical Feature Computation Engine for WSN Applications

  • Short Paper
  • Published:
Circuits, Systems, and Signal Processing Aims and scope Submit manuscript

Abstract

In this paper, we present a carry-save arithmetic- based coordinate rotation digital computer (CORDIC) engine for computing eight fundamental time-domain statistical features. These features are used commonly in association with major classifiers in remote health monitoring systems with an aim of executing them on a node of wireless sensor network (WSN). The engine computes all the eight features sequentially in \(3n\) clock cycles where \(n\) is the number of data samples. We further present a comparative analysis of the hardware complexity of our proposed architecture with an alternate architecture which does not use CORDIC (instead uses standalone array multiplier, divider, square rooter and logarithm converter). The hardware complexity of the two architectures presented in terms of full adder count reflects the effectiveness of using CORDIC for the given application. The engine was synthesized using the STMicroelectronics 130 nm technology library and occupied 205K NAND2 equivalent cell area and consumed 1 nW dynamic power @ 50 Hz as estimated using prime time. Therefore, the design can be applicable for low-power real-time operations within a WSN node.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10

Similar content being viewed by others

References

  1. A. Acharyya, K. Maharatna, B.M. Al-Hashmi, J. Reeve, Coordinate rotation based low complexity N-D FastICA algorithm and architecture. IEEE Trans. Signal Process. 59(8), 3997–4011 (2011)

    Article  MathSciNet  Google Scholar 

  2. H. Alemdar, C. Ersoy, Wireless sensor networks for healthcare: a survey. Elsevier Comput. Netw. 54(15), 2688–2710 (2010)

    Article  Google Scholar 

  3. D.D. Caro, M. Genovese, E. Napoli, N. Petra, A.G.M. Strollo, Accurate fixed point logarithm converter. IEEE Trans. Circuits Syst. II Express Briefs 61(7), 526–530 (2014)

  4. S. Chernbumroong, S. Cang, A. Atkins, H. Yu, Elderly activities recognition and classification for applications in assisted living. Expert Syst. Appl. 40(5), 1662–1674 (2013)

    Article  Google Scholar 

  5. M.D. Ercegovac, T. Lang, Digital Arithmetic (Morgan Kaufmann, Burlington, 2003), pp. 549–607

    Google Scholar 

  6. M. Ermes, J. Parkka, J. Mantyjarvi, I. Korhonen, Detection of daily activities and sports with wearable sensors in controlled and uncontrolled conditions. IEEE Trans. Inf. Technol. Biomed. 12(1), 20–26 (2008)

    Article  Google Scholar 

  7. E. Grass, B. Sarker, K. Maharatna, A dual-mode synchronous/asynchronous CORDIC processor, in Proceedings of the Eighth International IEEE Symposium on Asynchronous Circuits and Systems, Apr 2002, pp. 76–83

  8. Y.J. Hong, I.J. Kim, S.C. Ahn, H.G. Kim, Mobile health monitoring system based on activity recognition using accelerometer. Elsevier Simul. Model. Pract. Theory 18(4), 446–455 (2010)

    Article  Google Scholar 

  9. C.Y. Kang, E. Swartzlander, Digit-pipelined direct digital frequency synthesis based on differential CORDIC. IEEE Trans. Circuits Syst. I 53(5), 1035–1044 (2006)

    Article  Google Scholar 

  10. K. Kota, J.R. Cavallaro, Numerical accuracy and hardware tradeoffs for CORDIC arithmetic for special-purpose processors. IEEE Trans. Comput. 42(7), 769–779 (1993)

    Article  Google Scholar 

  11. R. Kunemund, H. Soldner, S. Wohlleben, T. Noll, Cordic processor with carry-save architecture, in Proceedings of the ESSCIRC 90, Sept 1990, pp. 193–196

  12. C.H. Lin, A.Y. Wu, Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications. IEEE Trans. Circuits Syst. I 52(11), 2385–2396 (2005)

    Article  MathSciNet  Google Scholar 

  13. K. Maharatna, E.B. Mazomenos, J. Morgan, S. Bonfiglio, Towards the development of next-generation remote healthcare system: some practical considerations, in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Seoul, May 2012, pp. 1–4

  14. P.K. Meher, J. Valls, T.B. Juang, K. Sridharan, K. Maharatna, 50 Years of CORDIC: algorithms, architectures, and applications. IEEE Trans. Circuits Syst. I 56(9), 1893–1907 (2009)

    Article  MathSciNet  Google Scholar 

  15. P. Nair, D. Kudithipudi, E. John, Design and implementation of a CMOS non-restoring divider, in Region 5 Conference, IEEE, 7–9 Apr 2006, pp. 211–217

  16. L. Vachhani, K. Sridharan, P.K. Meher, Efficient CORDIC algorithms and architectures for low area and high throughput implementation. IEEE Trans. Circuits Syst. II 56(1), 2385–2396 (2009)

    Article  Google Scholar 

  17. K.N. Vijeyakumar, V. Sumathy, P. Vasakipriya, A.D. Babu, FPGA implementation of low power high speed square root circuits, in IEEE International Conference on Computational Intelligence & Computing Research (ICCIC), 18–20 Dec 2012, pp. 1–5

Download references

Acknowledgments

This work was supported by the Information and Communication Technologies Theme of the European Union Seventh Framework Programme, under the project name “StrokeBack: Telemedicine system empowering stroke patients to fight back” (Grant Number 288692).

Author information

Authors and Affiliations

  1. Faculty of Physical Sciences and Engineering, University of Southampton, Southampton, SO17 1BJ, UK

    Dwaipayan Biswas & Koushik Maharatna

Authors
  1. Dwaipayan Biswas
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Koushik Maharatna
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Dwaipayan Biswas.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Biswas, D., Maharatna, K. A CORDIC-Based Low-Power Statistical Feature Computation Engine for WSN Applications. Circuits Syst Signal Process 34, 4011–4028 (2015). https://doi.org/10.1007/s00034-015-0041-5

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00034-015-0041-5

Keywords

Search

Navigation