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High-Speed RS(255, 239) Decoder Based on LCC Decoding

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Abstract

Algebraic Soft-Decision Decoding (ASD) of Reed–Solomon (RS) codes provides higher coding gain over the conventional hard-decision decoding (HDD), but involves high computational complexity. Among the existing ASD methods, the Low Complexity Chase (LCC) decoding is the one with the lowest implementation cost. LCC decoding is based on generating 2η test vectors, where η symbols are selected as the least reliable symbols for which hard-decision or the second more reliable decision are employed. Previous decoding algorithms for LCC decoders are based on interpolation and re-encoding techniques. On the other hand, HDD algorithms such as the Berlekamp–Massey (BM) algorithm or the Euclidean algorithm, despite of their low computational complexity, are not considered suitable for LCC decoding. In this paper, we present a new approach to LCC decoding based on one of these HDD algorithms, the inversion-less Berlekamp–Massey (iBM) algorithm, where the test vectors are selected for correction during decoding on occurrence of hard-decision decoding failure. The proposed architecture when applied to a RS(255, 239) code with η=3, saves a 20.5% and 2% of area compared to the LCC with factorization and a factorization-free decoder, respectively. In both cases, the latency is reduced by 34.5%, which is an increase of throughput rate in the same percentage since the critical path is the same in all the competing architectures. So an efficiency of at least 56% in terms of area-delay product can be obtained, compared with previous works. A complete RS(255, 239) LCC decoder with η=3 has been coded in VHDL and synthesized for implementation in Vitex-5 FPGA device, and by using SAED 90 nm standard cell library as well, and find a decoding rate of 710 Mbps and 4.2 Gbps and area of 2527 slices and 0.36 mm2, respectively.

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Authors and Affiliations

  1. Instituto de Telecomunicaciones y Aplicaciones Multimedia, Universidad Politécnica de Valencia, 46730, Gandia, Spain

    F. García-Herrero & J. Valls

  2. Department of Embedded Systems, Institute for Infocomm Research, 1 Fusionopolis Way, Singapore, 138632, Singapore

    P. K. Meher

Authors
  1. F. García-Herrero
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  2. J. Valls
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  3. P. K. Meher
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Correspondence to J. Valls.

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García-Herrero, F., Valls, J. & Meher, P.K. High-Speed RS(255, 239) Decoder Based on LCC Decoding. Circuits Syst Signal Process 30, 1643–1669 (2011). https://doi.org/10.1007/s00034-011-9327-4

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  • DOI: https://doi.org/10.1007/s00034-011-9327-4

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