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PVS: Combining specification, proof checking, and model checking

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Formal Methods in Computer-Aided Design (FMCAD 1996)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1166))

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Abstract

We claim that no single technique such as rewriting, BDDs, or model checking is effective for all aspects of hardware verification. Many examples need the careful integration of these techniques. We have shown some simple examples to illustrate the integration available in PVS. This combination of techniques has been applied to some larger examples such as an SRT divider and Rockwell-Collins AAMP series of processors. The automation available in PVS on these examples can be further improved through the use of more decision procedures (e.g., bit vectors) and better verification methodologies (e.g., abstraction, induction).

The development of PVS was funded by SRI International through IR&D funds. Various applications and customizations have been funded by NSF Grant CCR-930044, NASA, ARPA contract A721, and NRL contract N00015-92-C-2177. The PVS system is the result of developed as a collaborative effort involving Sam Owre, John Rushby, Mandayam Srivas, David Cyrluk, Pat Lincoln, Sree Rajan, Judy Crow, among many others.

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Authors and Affiliations

  1. Computer Science Laboratory, SRI International, 94025, Menlo Park, CA, USA

    N. Shankar

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  1. N. Shankar
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Mandayam Srivas Albert Camilleri

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© 1996 Springer-Verlag Berlin Heidelberg

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Shankar, N. (1996). PVS: Combining specification, proof checking, and model checking. In: Srivas, M., Camilleri, A. (eds) Formal Methods in Computer-Aided Design. FMCAD 1996. Lecture Notes in Computer Science, vol 1166. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0031813

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  • DOI: https://doi.org/10.1007/BFb0031813

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-61937-6

  • Online ISBN: 978-3-540-49567-3

  • eBook Packages: Springer Book Archive

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