A multiport page-memory architecture and a multiport disk-cache system

Abstract

Everlasting demands for solutions to ever growing computation problems and demands for efficient means to manage and utilize sophisticated information have caused an increase in the amount of data necessary to handle a job, while drastic reduction in CPU prices is encouraging massive parallel architectures for gigantic data processing. These trends are increasing the importance of a large shared buffer memory with 10³∼10⁴ simultaneously accessible ports. This paper proposes a multiport page buffer architecture that allows 10³∼10⁴ concurrent accesses and causes no access conflict nor suspension. It consists of a set of memory banks and multistaged switching networks with controllers that control each row of the networks. Consecutive words in each page are stored orthogonally across banks. Memory interleaving may be applied to improve access rate in consecutive retrievals. When used as a disk cache memory, it decreases the number of disk accesses and increases both the page transfer rate and the maximum number of concurrent page accesses.