Abstract
Various methods for mapping signal processing algorithms into systolic arrays have been developed in the past few years. In this paper, efficient scheduling techniques are developed for the partitioning problem, i.e. problems with size that do not match the array size. In particular, scheduling for the Locally Parallel-Globally Sequential (LPGS) technique and the Locally Sequential-Globally Parallel (LSGP) technique are developed. The scheduling procedure developed exploits the fact that after LPGS and LSGP partitioning, the locality constraints are less stringent allowing for more flexibility in the choice of algorithms and inter-processor communication. A flexible scheduling order is developed that is useful in evaluating the trade-off between execution time and size of storage buffers. The benefits of the scheduling techniques are illustrated with the help of matrix multiplication and least squares examples.
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This work was supported in part by the UCSD/NSF Integrated Circuits And Systems Research Center and by the ARMY Research Office under Grant No. DAAL-03-90-G-0095.
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Kuchibhotla, P., Rao, B.D. A methodology for fast scheduling of partitioned systolic algorithms. Journal of VLSI Signal Processing 10, 111–126 (1995). https://doi.org/10.1007/BF02407030
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DOI: https://doi.org/10.1007/BF02407030