Abstract
It is shown how the Gauß-Jordan Elimination algorithm for the Algebraic Path Problem can be implemented on a hexagonal systolic array of a quadratic number of simple processors in linear time. Special instances of this general algorithm include parallelizations of the Warshall-Floyd Algorithm, which computes the shortest distances in a graph or the transitive closure of a relation, and of the Gauß-Jordan Elimination algorithm for computing the inverse of a real matrix.
Zusammenfassung
Es wird dargestellt, wie man den gaus-Jordanschen Eliminationsalgorithmus für das algebraische Wegproblem auf einem hexagonalen systolischen Feld (systolic array) mit einer quadratischen Anzahl einfacher Prozessoren in linearer Zeit ausführen kann. Zu den Anwendungsbeispielen dieses allgemeinen Algorithmus gehört der Warshall-Floyd-Algorithmus zur Berechnung der kürzesten Wegen in einem Graphen oder zur Bestimmung der transitiven Hülle einer Relation sowie der Gauß-Jordansche Eliminationsalgorithmus zur Inversion reeller Matrizen.
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This work was initiated as a project in a lecture on Languages and VLSI design which Professor Karel Čulik II gave during his stay as a visiting professor at the Institutes for Information Processing, Technical University of Graz, Austria, in the summer semester 1983, and was later supported by the Computer Center Graz (Rechenzentrum Graz).
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Rote, G. A systolic array algorithm for the algebraic path problem (shortest paths; Matrix inversion). Computing 34, 191–219 (1985). https://doi.org/10.1007/BF02253318
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DOI: https://doi.org/10.1007/BF02253318
AMS subject classifications
CR categories and subject descriptors
- C.1.2[processor architectures]: multiple data stream architectures (multiprocessors)-systolic arrays
- G. 1.0 [numerical analysis]: general - parallel algorithms
- G. 1.3 [numerical analysis]: numerical linear algebra - matrix inversion
- G. 2.2 [discrete mathematics]: graph theory - path problems
- B.6.1 [logic design]:design styles - cellular arrays
- B.7.1 [integrated circuits]
- types and design styles - algorithms implemented in hardware
- VLSI (very large scale integration)