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Efficient VLSI array processing structures for adaptive quadratic digital filters

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Abstract

In this paper we introduce a class of efficient architectures for adaptive quadratic digital filters. These architectures are based on the LMS algorithm and use the rank compressed lower-upper (LU) triangular deomposition method. These architectures exhibit high parallelism as well as great modularity and regularity. We also consider affiliated VLSI array processing structures and compare these in terms of hardware cost and data throughput delay. For comparison purposes, the distributed arithmetic structures of adaptive quadratic filters are also included in the paper. Finally, the convergence performance of the adaptive quadratic filters is tested via benchmark simulation examples.

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Authors and Affiliations

  1. Communications and Digital Signal Processing (CDSP) Center, Department of Electrical and Computer Engineering, Northeastern University, 02115, Boston, Massachusetts, USA

    Yuang Lou & Chrysostomos L. Nikias

  2. Department of Electrical Engineering, University of Toronto, M5S1A4, Toronto, Canada

    Anastasios N. Venetsanopoulos

Authors
  1. Yuang Lou
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  2. Chrysostomos L. Nikias
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  3. Anastasios N. Venetsanopoulos
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Additional information

This work was supported by National Science Foundation Grant ECS-8601307.

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Lou, Y., Nikias, C.L. & Venetsanopoulos, A.N. Efficient VLSI array processing structures for adaptive quadratic digital filters. Circuits Systems and Signal Process 7, 253–273 (1988). https://doi.org/10.1007/BF01602100

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  • DOI: https://doi.org/10.1007/BF01602100

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