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Quadratic 0/1 optimization and a decomposition approach for the placement of electronic circuits

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Abstract

The placement problem in the layout design of electronic circuits consists of finding a nonoverlapping assignment of rectangular cells to positions on the chip so that wireability is guaranteed and certain technical constraints are met. This problem can be modelled as a quadratic 0/1-program subject to linear constraints. We will present a decomposition approach to the placement problem and give results above NP-hardness and the existence ofε-approximative algorithms for the involved optimization problems. A graph theoretic formulation of these problems will enable us to develop approximative algorithms. Finally we will present details of the implementation of our approach and compare it to industrial state of the art placement routines.

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References

  • M.R. Garey and D.S. Johnson,Computers and Intractability. A Guide to the Theory ofNP-Completeness (Freeman, New York, 1979).

    Google Scholar 

  • F.M. Johannes, K.M. Just and K.J. Antreich, “On the force placement of logic arrays,”Proceedings of the 6-th European Conference on Circuit Theory and Design (1983) pp. 203–206.

  • K.M. Just and J.M. Kleinhans, “On the simultaneous placement of modules of integrated circuits,”AEÜ (1985) 217–224.

  • R.M. Karp,Reducibility Among Combinatorial Problems (Plenum, New York, 1972).

    Google Scholar 

  • J.M. Kleinhans, G. Sigl and F.M. Johannes, “Gordian: A new global optimization/rectangle dissection method for cell placement,”IEEE International Conference on CAD ICCAD-88 (1988) 506–509.

  • J.M. Kleinhans, G. Sigl, F.M. Johannes and K.J. Antreich, “Gordian: VLSI placement by quadratic programming and slicing optimization,”IEEE Transactions on Computer Aided Design 10 (1991).

  • U. Lauther, “A min-cut placement algorithm for general cell assemblies based on a graph representation,”ACM/ICEE Proceedings of the 16th DAC (1979) 1–10.

  • T. Lengauer,Combinatorial Algorithms for Integrated Circuit Layout (Wiley—Teubner, New York, 1990).

    Google Scholar 

  • R.Müller, “Hierarchisches Floorplanning mit integrierter globaler Verdrahtung'„ Dissertation, Universität GH Paderborn (Paderborn, 1990).

    Google Scholar 

  • R. Weismantel, “Plazieren von Zellen: Theorie und Lösung eines quadratischen 0/1 Optimierungsproblems,” Dissertation, Technische Universität Berlin (Berlin, 1992).

    Google Scholar 

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Jünger, M., Martin, A., Reinelt, G. et al. Quadratic 0/1 optimization and a decomposition approach for the placement of electronic circuits. Mathematical Programming 63, 257–279 (1994). https://doi.org/10.1007/BF01582072

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  • DOI: https://doi.org/10.1007/BF01582072

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