Abstract
A new bit-serial architecture for implementation of high order FIR filters is introduced, as well as example FPGA and CMOS realizations. This structure exploits the simplicity of coefficients that consist of two power-of-two terms to yield efficient implementations. Quantization effects are discussed and a simple block scaling method for reducing rounding and truncation noise in high order filters is also presented.
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Lim, Y.C., Evans, J.B. & Liu, B. An efficient bit-serial FIR filter architecture. Circuits Systems and Signal Process 14, 639–651 (1995). https://doi.org/10.1007/BF01213960
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DOI: https://doi.org/10.1007/BF01213960