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An approach to automating the verification of compact parallel coordination programs. I

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Summary

A class of parallel coordination programs for a shared memory asynchronous parallel processor is considered. These programs use the operation Fetch & Add which is the basic primitive for the NYU-Ultracomputer. A correctness proof for the considered programs must be done for arbitrary number N of processing elements since the Ultracomputer design includes thousands of PEs.

A reachability set description (RSD) is introduced, in which all reachable states of a program (exponential function of N) are collapsed into a fixed number of metastates. The transitions between these metastates are then specified. By using such notation, it becomes feasible to prove various temporal properties of a parallel program, in particular, the absence of livelock. The concept of a compact parallel program is introduced. Roughly speaking a parallel program executed by N PEs is compact if there exists a boundary T independent of N such that any state of this program is reachable within time T. Compactness may also be understood as the finiteness of the expansion for the strongest invariant in the least fixpoint theory, where such finiteness is uniform over N. A program that builds RSDs for compact parallel programs and examples of proofs generated by this program are discussed.

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This work was supported in part by the Applied Mathematical Sciences Program of the U.S. Department of Energy under Contract No. DE-AC02-76ER03077, and in part by the National Science Foundation under Grant No. NSF-MCS79-21258

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Lubachevsky, B.D. An approach to automating the verification of compact parallel coordination programs. I. Acta Informatica 21, 125–169 (1984). https://doi.org/10.1007/BF00289237

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