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High Throughput Novel Architecture of SIT Cipher for IoT Application

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Nanoelectronics, Circuits and Communication Systems

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 692))

Abstract

The advancement in network connectivity and data handling capabilities shows the tremendous growth of Internet of things (IoT) in physical life. The number of connected devices has been increasing in IoT applications, left severe security concerns. The problem of providing security solutions to resource-constrained devices leads to lightweight cryptographic algorithms. Secure IoT (SIT) is one of the lightweight cryptographic algorithm follows SPN and Feistel structure. SIT cipher works on 64-bit block and 64-bit key size. In this chapter, an efficient pipelined architecture of SIT lightweight block cipher has been proposed. Operating frequency of this proposed work has been improved by 17% and also throughput improved by more than 180% in comparison with LEA lightweight block cipher.

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References

  1. Xu T, Wendt JB, Potkonjak M (2015) Security of IoT systems: design challenges and opportunities. IEEE/ACM International Conference on Computer-Aided Design. Dig. Tech. Pap. ICCAD, vol 2015, pp 417–423

    Google Scholar 

  2. Gubbi J, Buyya R, Marusic S, Palaniswami M (2013) Internet of Things (IoT): a vision, architectural elements, and future directions. Futur Gener Comput Syst 29(7):1645–1660

    Article  Google Scholar 

  3. Singh P, Acharya B, Chaurasiya RK (2019) A comparative survey on lightweight block ciphers for resource constrained applications. Int J High Perform Syst Archit 8(4):250–270

    Article  Google Scholar 

  4. Usman M, Ahmed I, Imran M, Khan S, Ali U (2017) SIT: a lightweight encryption algorithm for secure internet of things. Int J Adv Comput Sci Appl 8(1):1–10

    Google Scholar 

  5. Mohd BJ, Hayajneh T, Vasilakos AV (2015) A survey on lightweight block ciphers for low-resource devices: Comparative study and open issues. J Netw Comput Appl 58:73–93

    Article  Google Scholar 

  6. Banu JS, Vanitha M, Vaideeswaran J, Subha S (2013) Loop parallelization and pipelining implementation of AES algorithm using OpenMP and FPGA. 2013 IEEE international conference emerging trends in computing, communication and nanotechnology, ICE-CCN 2013, pp 481–485

    Google Scholar 

  7. Hong D et al (2006) HIGHT: a new block cipher suitable for low-resource device. Lect. Notes Comput. Sci. (including Subser. Lect. Notes Artif. Intell. Lect. Notes Bioinformatics), vol 4249 LNCS, pp 46–59

    Google Scholar 

  8. Shibutani K, Isobe T, Hiwatari H, Mitsuda A, Akishita T, Shirai T (2011) Piccolo: an ultra-lightweight blockcipher. Lect. Notes Comput. Sci. (including Subser. Lect. Notes Artif. Intell. Lect. Notes Bioinformatics), vol 6917 LNCS, pp 342–357

    Google Scholar 

  9. Berger TP, Francq J, Minier M, Thomas G (2016) Extended generalized Feistel networks using matrix representation to propose a new lightweight block cipher: lilliput. IEEE Trans Comput 65(7):2074–2089

    Article  MathSciNet  Google Scholar 

  10. Lee D, Kim DC, Kwon D, Kim H (2014) Efficient hardware implementation of the lightweight block encryption algorithm LEA. Sensors (Switzerland) 14(1):975–994

    Article  Google Scholar 

  11. Li L, Liu B, Wang H (2016) QTL: a new ultra-lightweight block cipher. Microprocess Microsyst 45:45–55

    Article  Google Scholar 

  12. Kaps JP (2008) Chai-tea, cryptographic hardware implementations of xtea. In: International conference on cryptology in India Springer, Berlin, pp 363–375

    Google Scholar 

  13. Wheeler DJ, Needham RM (1995) Tea, a tiny encryption algorithm. Lect. Notes Comput. Sci. (including Subser. Lect. Notes Artif. Intell. Lect. Notes Bioinformatics), vol 1008, pp 363–366

    Google Scholar 

  14. Gong Z, Nikova S, Law YW (2011) KLEIN : a new family of lightweight block ciphers. In: International workshop on radio frequency identification: security and privacy issues. Springer, Berlin, pp 1–18

    Google Scholar 

  15. Mishra Z, Ramu G, Acharya B (2019) Hight speed low area VLSI architecture for LEA encryption algorithm. In: Proceedings of the third international conference on microelectronics, computing and communication systems, pp 155–160. Springer, Singapore

    Google Scholar 

  16. Sekhar A (2017) Design of a new lightweight encryption for embedded security. Int Res J Eng Technol 4(6):398–402

    MathSciNet  Google Scholar 

  17. De Canni C (2009) “KATAN & KTANTAN—a family of small and efficient hardware-oriented block ciphers. In: International workshop on cryptographic hardware and embedded systems, pp 272–288. Springer, Berlin

    Google Scholar 

  18. Soltani A, Sharifian S (2015) An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA. Microprocess Microsyst 39(7):480–493

    Article  Google Scholar 

  19. Engels D, Fan X, Gong G, Hu H, Smith EM (2010) Hummingbird : ultra-lightweight cryptography for resource-constrained devices. In: International conference on financial cryptography and data security, pp 3–18. Springer, Berlin

    Google Scholar 

  20. Imran M, Rashid M, Shafi I (2018) Lopez Dahab based elliptic crypto processor (ECP) over GF(2163) for low-area applications on FPGA. 2018 International Conference on Engineering Emerging Technologies. ICEET 2018, vol 2018, pp 1–6

    Google Scholar 

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Acknowledgements

This work has been carried out under Information Security Education Awareness (ISEA) project phase – II & SMDP-C2SD project funded by Ministry of Electronics and Information Technology (MeitY), Govt. of India in the Department of Electronics and Communication Engineering at National Institute of Technology Raipur, India. Authors are thankful to the Ministry for the facilities provided under this project.

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Correspondence to Bibhudendra Acharya .

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Mishra, Z., Mishra, S., Acharya, B. (2021). High Throughput Novel Architecture of SIT Cipher for IoT Application. In: Nath, V., Mandal, J. (eds) Nanoelectronics, Circuits and Communication Systems. Lecture Notes in Electrical Engineering, vol 692. Springer, Singapore. https://doi.org/10.1007/978-981-15-7486-3_26

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  • DOI: https://doi.org/10.1007/978-981-15-7486-3_26

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-15-7485-6

  • Online ISBN: 978-981-15-7486-3

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