Abstract
This paper presents an innovative approach for testing the core components in the multi-core system-on chip framework by scheduling the tasks assigned for the Core-Under-Test to one of the remaining cores in the system. Real-time task scheduling in multi-core/processor systems always remains the NP-Hard problems. In multi-core Real time systems, a faulty core can be tolerated by way of executing two versions (primary and backup) of a task in two different cores. The Genetic Algorithms provides an innovative and heuristic approach of scheduling both primary and backup tasks. The work presented in this paper shows the optimal utilization of all the available cores for functional operation at a given time in a Multi-Core System environment by scheduling and executing all the tasks arrived for execution.
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Prasad Acharya, G., Asha Rani, M. (2016). Fault-Tolerant Multi-core System Design Using PB Model and Genetic Algorithm Based Task Scheduling. In: Satapathy, S., Rao, N., Kumar, S., Raj, C., Rao, V., Sarma, G. (eds) Microelectronics, Electromagnetics and Telecommunications. Lecture Notes in Electrical Engineering, vol 372. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2728-1_41
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DOI: https://doi.org/10.1007/978-81-322-2728-1_41
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