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Real-Time Signal Processing on Field Programmable Gate Array Hardware

  • Chapter
Springer Handbook of Systematic Musicology

Part of the book series: Springer Handbooks ((SHB))

Abstract

Over the last 50 years, advances in high-speed digital signal processing (GlossaryTerm

DSP

) and numerical methods for audio signal processing in general were fueled by the rising processing capabilities of personal computers (GlossaryTerm

PC

s). Added to this was the advent of specialized coprocessing platforms like general purpose graphics processing units (GlossaryTerm

GPGPU

s), central processing unit (GlossaryTerm

CPU

)-based accelerators like Intel's Xeon Phi platforms as well as high-performance digital signal processing (GlossaryTerm

DSP

) chips like Analog Devices' TigerSHARC. Still, there are applications that are not realizable on the mentioned devices in real time or even close to real time. This chapter gives an introduction to field programmable gate array (GlossaryTerm

FPGA

) hardware, a flexible computing platform with massively parallel logic capability that is applicable for problems of high data throughput, high clock rates and high parallelism. After an introduction to the basic structure of FPGAs, several features that enable high-throughput DSP applications are highlighted. An introduction to development platforms as well as the development methodology is given, along with an overview of current FPGA devices and their specific capabilities. Two application examples and an outlook and summary complete this chapter.

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Abbreviations

1-D:

one-dimensional

1C:

one's complement

2-D:

two-dimensional

2C:

two's complement

3-D:

three-dimensional

ADC:

analog-to-digital converter

ALM:

adaptive logic module

ASIC:

application-specific integrated circuit

ASSP:

application-specific standard part

BC:

boundary condition

BLAS:

basic linear algebra subprograms

BRAM:

block RAM

CAD:

computer-aided design

CFL:

Courant–Friedrichs–Levy

CLB:

configurable logic block

codec:

coder-decoder

CPU:

central processing unit

DAC:

digital-to-analog converter

DDR:

double data rate

DIY:

do-it-yourself

DSP:

digital signal processing

EEPROM:

electrically erasable programmable read-only memory

EPROM:

erasable programmable read-only memory

FD:

finite difference

FDTD:

finite-difference time domain

FFT:

fast Fourier transform

FFTW:

fastest Fourier transform in the West

FIFO:

first in/first out

FIR:

finite impulse response

FMC:

FPGA mezzanine card

FPGA:

field programmable gate array

FSM:

finite-state machine

GPGPU:

general purpose graphics processing unit

GUI:

graphical user interface

HDL:

hardware description language

HLS:

high-level synthesis

HPC:

high-performance computing

I/O:

input/output

I2S:

inter-IC sound

IIR:

infinite impulse response

IL:

interface layer

IP:

intellectual property

LTI:

linear time-invariant

LUT:

look-up table

MAC:

multiply-and-accumulate

MoR:

model routing layer

NTT:

number theoretic transform

PCIe:

peripheral component interconnect express

PCM:

pulse code modulation

PC:

personal computer

PDE:

partial differential equation

PLD:

programmable logic device

PROMS:

programmable read-only memory

RAM:

random access memory

RSV:

reserved

RTL:

register transfer level

SATA:

serial advanced technology attachment

SPI:

serial peripheral interface

TFLOPS:

tera floating point operations per second

TMACS:

tera multiply-and-accumulates per second

ucf:

user constraint file

USB:

universal serial bus

VHDL:

very high speed integrated circuit hardware description language

WDF:

wave digital filter

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  1. Institute of Systematic Musicology, University of Hamburg, Neue Rabenstr. 13, 20354, Hamburg, Germany

    Florian Pfeifle

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  1. Institute of Systematic Musicology, University of Hamburg, Neue Rabenstr. 13, 20354, Hamburg, Germany

    Rolf Bader

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Pfeifle, F. (2018). Real-Time Signal Processing on Field Programmable Gate Array Hardware. In: Bader, R. (eds) Springer Handbook of Systematic Musicology. Springer Handbooks. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-55004-5_20

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