Planar Circuit Complexity and The Performance of VLSI Algorithms +

Abstract

In 1979 Thompson [1] reported that, under a suitable model for VLSI chips, the product AT² of chip area and time T to compute the Fast Fourier Transform on n inputs must satisfy AT² = Ω(n²). His model accounts for the chip area used by wires as well as for computational elements. He extended these results in [2] and in addition examined the sorting problem. Brent and Kung [3] introduced a somewhat different model for VLSI chips in which the area occupied by wires and circuit elements is convex. They demonstrate that AT² = Ω(n²) to multiply two n-bit integers, a result obtained with the original model of Thompson by Abelson and Andreae [4]. Brent and Kung show that A = Ω (n) and they present algorithms that come close to meeting their lower bounds. Savage [5] obtained bounds of AT² = Ω(p⁴) with both models for pxp matrix multiplication, inversion and transitive closure. Algorithms previously given by Kung and Leiserson [6] and Guibas et al. [7] were shown to be optimal. Preparata and Yuillemin [8] subsequently introduced a family of optimal matrix multiplication algorithms for Ω(1) ≤ T ≤ 0(n),

This work was supported in part by the National Science Foundation under grant MCS 76-20023, by the University of Paris-Sud, Orsay and by INRIA, Rooquencourt, France. Preparation was supported in part by NSF Grant ECS 80-24637.