Abstract
We present one-dimensional systolic arrays for performing two- or higher-dimensional convolution and resampling. These one-dimensional arrays are characterized by the fact that their I/0 bandwidth requirement is independent of the size of the convolution kernel. This contrasts with alternate two-dimensional array solutions, for which the I/0 bandwidth must increase as the kernel size increases. The proposed architecture is ideal for VLSI implementation—an arbitrarily large kernel can be handled by simply extending the linear systolic array with simple processors of the same type, so that one processor corresponds to each kernel element.
H.T. Kung was supported in part by the Office of Naval Research under ConÂtracts N00014-76-C-0370, NR 044-422 and N00014-80-C-0236, NR 048-659
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References
H.T. Kung: Why Systolic Architectures? Computer Mag. 15, 37–46 (January 1982)
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Kung, H.T., Picard, R.L. (1984). One-Dimensional Systolic Arrays for Multidimensional Convolution and Resampling. In: Fu, Ks. (eds) VLSI for Pattern Recognition and Image Processing. Springer Series in Information Sciences, vol 13. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-47523-8_2
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DOI: https://doi.org/10.1007/978-3-642-47523-8_2
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