Abstract
Physical(ly) Unclonable Functions (PUFs) are expected to represent a solution for secure ID generation, authentication, and other important security applications. Researchers have developed several kinds of PUFs and self-evaluated them to demonstrate their advantages. However, both performance and security aspects of some proposals have not been thoroughly and independently evaluated. Third-party evaluation is important to discuss whether a proposal performs according to what the developers claim, regardless of any accidental bias. In this paper, we focus on Glitch PUFs (GPUFs) that use an AES S-Box implementation as a glitch generator, as proposed by Suzuki et al. [1]. They claim that this GPUF is one of the most practically feasible and secure delay-based PUFs. However, it has not been evaluated by other researchers yet. We evaluate GPUFs implemented on FPGAs and present three novel results. First, we clarify that the total number of challenge-response pairs of GPUFs is 219, instead of 211. Second, we show that a GPUF implementation has low robustness against voltage variation. Third, we point out that the GPUF has “weak” challenges leading to responses that can be more easily predictable than others by an adversary. Our results indicate that GPUFs that use the AES S-Box as the glitch generator present almost no PUF-behavior as both reliability and uniqueness are relatively low. In conclusion, our case study on FPGAs suggests that GPUFs should not use the AES S-Box as a glitch generator due to performance and security reasons.
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Yamamoto, D., Hospodar, G., Maes, R., Verbauwhede, I. (2012). Performance and Security Evaluation of AES S-Box-Based Glitch PUFs on FPGAs. In: Bogdanov, A., Sanadhya, S. (eds) Security, Privacy, and Applied Cryptography Engineering. SPACE 2012. Lecture Notes in Computer Science, vol 7644. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-34416-9_4
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DOI: https://doi.org/10.1007/978-3-642-34416-9_4
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